Week7 - Week 7 Concurrent Programming: Thread...

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Week 7 Concurrent Programming: Thread Synchronization CS 180 Sunil Prabhakar Department of Computer Science Purdue University Tuesday, December 8, 2009
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Announcements Exam 1 tonight 6:30 pm - 7:30 pm MTHW 210 2 Tuesday, December 8, 2009
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Outcomes Understand race conditions Critical sections and mutual exclusion Synchronization mechanism synchronized methods, block of code wait() and notify() Understand potential problems busy waiting deadlock livelock 3 Tuesday, December 8, 2009
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Thread Scheduling Remember Once a thread is runnable it can be scheduled at any time It is hard to predict the actual ordering With multiple threads, we must ensure that any possible interleaving of threads would still be a correct execution 4 Tuesday, December 8, 2009
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Race Conditions If the result of a computation changes depending upon the actual ordering of threads we call it a race condition . Can occur even with very simple concurrent programs. Consider a program that simply increments a single variable, count 100000 times the task is divided among multiple threads 5 Tuesday, December 8, 2009
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Race Example 6 public class RaceCondition extends Thread { private static int counter = 0; public static final int THREADS = 4; public static final int COUNT = 10000000; public static void main(String[] args){ RaceCondition[] threads = new RaceCondition[THREADS]; for ( int i=0;i<THREADS;i++) { threads[i] = new RaceCondition(); threads[i].start(); } try { for ( int i=0;i<THREADS;i++) threads[i].join(); } catch (InterruptedException e) { e.printStackTrace(); } System.out.println(“Counter: “ + counter); } public void run(){ for ( int i=0;i<COUNT/THREADS;i++) counter++; } } Tuesday, December 8, 2009
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Race Without multiple threads, always correct. With multiple threads, often incorrect! Why? multiple threads modifying the same value counter++ is not atomic Atomic operations A java statement translates to multiple machine level statements the thread can be swapped in the middle of these machine level statements 7 Tuesday, December 8, 2009
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CPU The memory hierarchy 8 ALU Cache Cache (MB) Registers Main Memory (GB) Speed Size Cost Tuesday, December 8, 2009
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Multi Core possibility Cache (MB) Core ALU Cache Registers Main Memory (GB) Core ALU Cache Registers CPU Tuesday, December 8, 2009
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CPU Multi Core possibility 2 Cache (MB) Main Memory (GB) Core ALU Registers Core ALU Registers Tuesday, December 8, 2009
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CPU Multi CPU possibility CPU ALU Cache Registers Main Memory (GB) ALU Cache Registers Cache (MB) Cache (MB) ALU Cache Registers Program Data Tuesday, December 8, 2009
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Atomic operations and Caching Data is operated on in ALUs register = count; register++; count = register; Thus if a thread is swapped out just before the last statement, and another thread swapped in, then we have a “lost update” The memory hierarchy caches data values.
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This note was uploaded on 03/26/2012 for the course STAT 350 taught by Professor Staff during the Spring '08 term at Purdue.

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Week7 - Week 7 Concurrent Programming: Thread...

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