Timing0 - Practical Considerations In text book or ideal...

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Practical Considerations In text book or ideal world Signals change state or propagate though combinational or sequential networks In zero time At every turn real world signals encounter physics of practical devices Thousands of dead physicists are there just waiting for us If we are to design and build reliable and robust systems We must understand when, where, how, and why Such physical affects occur Once we gain such understanding Design around or compensate for potential problems Can incorporate them into our models To determine How they are affecting our system If our design approach for mitigating affects Has proven successful We will first look at combinational logic Then move on to sequential circuits Part 1 Timing in Combinational Logic – introduction Now want to examine techniques for modeling Real world affects Such affects focus (result primarily from) on Consequences of inherent parasitic devices Such devices comprise passive components R, L, C Devices present in Systems built of discrete components Programmable logic devices Internal to device Getting onto or off of device LSI and VLSI circuits Timing and Delays When modeling designs to study and to test real world behaviour Must understand and work with physical world - 1 of 37 -
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That alters behaviour from the ideal Such effects include signal delays In our studies of combinational logic We find several fundamental timing issues we need to consider Rise / Fall Times Propagation delay Race Conditions These will carry forward to work with sequential circuits We will also examine Potential root causes for such issues Affects on our circuits Some basic models In later section Will see how to incorporate such affects into Verilog model Let’s briefly review each of timing issues Fundamental Attributes Textbook waveforms Change state in zero time Move through system at infinite speed Real-world signals not quite as efficient Will begin our study with look at simple delays Such delays are first step away from textbook behaviour Rise Time, Fall Time, and Turn-Off Delays These delays give measure of time signal takes To change state From 0 to 1 or 1 to 0 Tristate part to cease driving Consider the following signal We measure rise and fall time at - 2 of 37 -
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10% and 90% points Time called rise time and fall time Two times not always symmetrical Specify τ r and τ f or τ rise and τ fall Problem If rise / fall times too long Gate no longer acts as switch instead becomes poor amplifier Enters what is called metastable region Will discuss in more detail shortly Modeling Rise Time, Fall Time, and Turn-Off Delays To incorporate the time required for a signal to change state Verilog supports including device rise time, fall time into model The syntax for these is given as Illustrated in following code fragment Syntax # (rise time, fall time) device; and #(3,4)myAnd(out, in0, in1); When working with busses or simply individual signals Connected utilizing tristate devices Time for device output to turn-off once control is deasserted
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Timing0 - Practical Considerations In text book or ideal...

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