lecture02

lecture02 - ECE252 Microprocessors Spring 2011 Lecture 02:...

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Jie Hu, ECE/NJIT, ECE252 L02- ECE252 Microprocessors Spring 2011 Lecture 02: 68000 Microprocessor Architecture Jie Hu http://web.njit.edu/~jhu/ece252/002
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Jie Hu, ECE/NJIT, ECE252 L02- Block Diagram of Macintosh 512K Motherboard Processor 68000 I/O Interface 6522 Real- time clock Serial I/O 8530 Floppy disk controller System ROM RAM buffers and Mux PAL decoders Dynamic RAM 512KB Sound logic Video logic Speaker Video display Control signals Modem Printer Mouse Keyboard System bus Disk drive
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Jie Hu, ECE/NJIT, ECE252 L02- Review of Last Lecture Evolution of computers First generation (vacuum tubes), 1946-1958 Second generation (transistor), 1959-1964 Third generation (integrated circuit), 1965-1970 Fourth generation (LSI/VLSI, Microprocessor), 1971-present Microprocessor based systems CPU, memory, timing unit, interrupt circuitry, I/O, peripherals, … Microprocessor operation Reset Fetch Decode Execute Fetch Programming languages HLL, assembly, and machine languages Developing software for 68000 microprocessor HELLO program
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Jie Hu, ECE/NJIT, ECE252 L02- Today’s Lecture Functional Description of the 68000 Programming Model of the 68000 Composing Solution for Programming Assignments Number Systems and Base Conversion Signed Number Representations ASCII Table
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Jie Hu, ECE/NJIT, ECE252 L02- 68000 Microprocessor Pin Layout 64 D 5 63 D 6 62 D 7 61 D 8 60 D 9 59 D 10 58 D 11 57 D 12 56 D 13 55 D 14 54 D 15 53 GND 52 A 23 51 A 22 50 A 21 49 V CC 48 A 20 47 A 19 46 A 18 45 A 17 44 A 16 43 A 15 42 A 14 41 A 13 40 A 12 39 A 11 38 A 10 37 A 9 36 A 8 35 A 7 34 A 6 33 A 5 68000 CPU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 D 4 D 3 D 2 D 1 D 0 AS UDS LDS R/W DTACK BG BGACK BR V CC CLK GND HALT RESET VMA E VPA BERR IPL 2 IPL 1 IPL 0 FC 2 A 1 A 2 A 3 A 4 FC 1 FC 0
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Jie Hu, ECE/NJIT, ECE252 L02- 68000 Microprocessor Pin Input/Output Signals D 15 –D 0 AS UDS LDS R/W DTACK BG BGACK BR V CC CLK HALT RESET VMA E VPA BERR IPL 2 IPL 1 IPL 0 FC 2 FC 1 FC 0 V CC GND GND 68000 CPU A 23 –A 1 +5V Data bus Address bus Asynchronous bus control Bus arbitration control Interrupt control System control 6800 peripheral control Processor status
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Jie Hu, ECE/NJIT, ECE252 L02- 68000 Microprocessor Pin Signals: Summary Supply Voltage/Ground: Vcc, GND Clock: CLK Address bus: A 23 -A 1 Data bus: D 15 -D 0 Asynchronous bus control: Address Strobe (AS), Read/Write (R/W), Upper/Lower Data Strobe (UDS, LDS), Data Transfer Acknowledge (DTACK) Bus arbitration control: Bus Request (BR), Bus Grant (BG), Bus Grant Acknowledge (BGACK) Interrupt control: IPL 0 , IPL 1 , IPL 2 System control: Bus Error (BERR), Reset (RESET), Halt (HALT) M6800 peripheral control: Enable (E), Valid Peripheral Address (VPA), Valid Memory Address (VMA) Processor status: FC 0 , FC 1 , FC 2
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lecture02 - ECE252 Microprocessors Spring 2011 Lecture 02:...

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