lecture15

lecture15 - ECE252 Microprocessors Spring 2011 Lecture 15:...

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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .1 ECE252 Microprocessors Spring 2011 Lecture 15: Exception Handler Jie Hu http://web.njit.edu/~jhu/ece252/002
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .2 Block Diagram of Macintosh 512K Motherboard Processor 68000 I/O Interface 6522 Real- time clock Serial I/O 8530 Floppy disk controller System ROM RAM buffers and Mux PAL decoders Dynamic RAM 512KB Sound logic Video logic Speaker Video display Control signals Modem Printer Mouse Keyboard System bus Disk drive
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .3 Review of Last Lecture Processor execution states Privilege states Exception processing sequence Exception Processing Processor execution states Privilege states Exception processing sequence In-Class Programming Practice Fibonacci Number
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .4 Today’s Lecture Multiple Exceptions Special exceptions Group 0: Reset, Bus Error, Address Error Group 1: Trace, Interrupt, Illegal, Privilege Group 2: Trap, Trapv, CHK, Divide-by-zero Exception handler
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .5 Multiple Exceptions Single exception is handled by deviating from normal execution state to exception state, and then return back to normal state What if multiple exceptions happened simultaneously? what is microprocessors’ strategy to handling multiple exceptions? what policy should be enforced? What if new exceptions happened during the handling of a previous exception? what is microprocessors’ strategy? what policy should be enforced?
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .6 Prioritized Exceptions in 68K Group Exception Priority 0 Reset (highest) Bus error Address error (lowest) 1 Trace (highest) Interrupt Illegal Privilege (lowest) 2 Trap (all four have same priority) Trapv CHK Zero divide
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .7 Multiple Exception Processing User Program (Tracing enabled) EXG D0, D1 Trace exception handler s a v e c o n t x r te i u p d g Interrupt exception handler
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .8 Exception Group 0: Reset Reset exception must be generated at power-on by external system hardware by pulling !RESET and !HALT pins to ground for at least 100ms Handling Reset exception SSP and PC are loaded from vector table (locations referenced by vectors 0 and 1) interrupt priority mask of SR is set to level 7 to inhibit all lower interrupts from occurring during reset S bit of SR is set so that the processor enters supervisor state T (tracing) bit of SR is cleared to disable tracing mode Note: if any current processing is caught by Reset exception, the processing is terminated and never resumed.
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L15-Exception. .9 Reset Exception Vector Contents 0000 9000 0000 0400 Address Data 000000 000002 000004 000006
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lecture15 - ECE252 Microprocessors Spring 2011 Lecture 15:...

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