lecture20

lecture20 - Jie Hu, ECE/NJIT, Spring 2011 ECE252...

Info iconThis preview shows pages 1–11. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.1 ECE252 Microprocessors Spring 2011 Lecture 20: Memory System Design Jie Hu http://web.njit.edu/~jhu/ece252/002 Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.2 Block Diagram of Macintosh 512K Motherboard Processor 68000 I/O Interface 6522 Real- time clock Serial I/O 8530 Floppy disk controller System ROM RAM buffers and Mux PAL decoders Dynamic RAM 512KB Sound logic Video logic Speaker Video display Control signals Modem Printer Mouse Keyboard System bus Disk drive Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.3 Review of Last Lecture Memory System Design Bus buffering Accessing memory Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.4 Todays Lecture Memory System Design Memory address decoder Partial-Address decoding Design with available memories !DTACK Generation Circuit Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.5 Memory Map in Macintosh 512K 512KB RAM 64KB ROM SCC Read SCC Write IWM VIA $000000 $080000 $400000 $410000 $900000 $A00000 $B00000 $C00000 $D00000 $E00000 $E80000 $F00000 Serial I/O 8530 System ROM Dynamic RAM 512KB I/O Interface 6522 Floppy disk controller $FFFFFF 16MB Memory Space Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.6 Why Memory Address Decoder? Different types of memories (ROM, RAMs) and I/O devices are mapped into processors memory/addressing space (16MB in 68000) Addressing issues: Given an address, which device (i.e., ROM, RAM, I/O devices) is the processor intending to access? If its to memories and the memory (ROM, RAMs) consists of multiple modules, which module should be enabled/selected? Memory address decoder : to monitor the state of the address bus and determine when the memory chips/modules should be enabled. e.g., whether current address is accessing the ROM chip or the RAM chip? Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.7 Memory Address Decoder Memory Address Decoder RAM or EPROM AS CS SEL Address bus Data bus Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.8 Timing Diagram of Memory Address Decoder AS A 23-A 1 SEL Valid address Memory address decoding delay Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.9 Designing Memory Address Decoder Design problem Premise: the physical memory (ROMs or RAMs) is to be mapped into a particular region of processors addressing space Requirement: the memory address decoder enables/selects the corresponding memory devices upon receiving a memory address Designing memory address decoder First step: determine how many address lines (bits) are needed just for the memory device itself Second step: use the remaining address lines (of 23 address lines in 68000) for the memory address decoder to generate Enable/Select signals (to memory chips) Jie Hu, ECE/NJIT, Spring 2011 ECE252 L20-Memory.10 Memory Address Decoder for a Single Range Design example 8.1: A 64K words (128KB) RAM is to be interfaced to a 68000-based system, so that the first...
View Full Document

Page1 / 39

lecture20 - Jie Hu, ECE/NJIT, Spring 2011 ECE252...

This preview shows document pages 1 - 11. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online