lecture22

lecture22 - ECE252 Microprocessors Spring 2011 Lecture 22:...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.1 ECE252 Microprocessors Spring 2011 Lecture 22: I/O System Design Jie Hu http://web.njit.edu/~jhu/ece252/002
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.2 Block Diagram of Macintosh 512K Motherboard Processor 68000 I/O Interface 6522 Real- time clock Serial I/O 8530 Floppy disk controller System ROM RAM buffers and Mux PAL decoders Dynamic RAM 512KB Sound logic Video logic Speaker Video display Control signals Modem Printer Mouse Keyboard System bus Disk drive
Background image of page 2
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.3 Review of Last Lecture I/O System Design Memory-mapped I/O Parallel data transfer
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.4 Today’s Lecture I/O System Design Parallel data transfer Serial data transfer
Background image of page 4
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.5 Parallel Data Transfer: The 6821 PIA Parallel data transfer: transfer all bits of a byte or a word at the same time using multiple signal wires 6821 peripheral interface adapter (PIA) initially designed for 6800-based systems low speed support 2 separate 8-bit ports, port A and port B each port has control register, peripheral (data) register, and data direction register (DDR) each of 8 bits of both port A and port B can be configured as input or output through the DDR
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.6
Background image of page 6
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.7 6821 Programmer’s Model Control register bit RS 1 RS 0 CRA-2 CRB-2 0 0 1 X Peripheral register A 0 0 0 X Data direction register A 0 1 X X Control register A 1 0 X 1 Peripheral register B 1 0 X 0 Data direction register B 1 1 X X Control register B Selected register
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.8 6821 Registers Control register A/B (8-bit) b0: interrupt request enable/disable b1: determine active CA1/CB1 transition setting b2: DDR access (0: DDR, 1: output register) b3,b4,b5: CA2/CB2 as input or output, select interrupt/strobing options b6,b7: interrupt flags Data direction register (DDR) set corresponding bit in DDR to 1 to make a particular bit of the port an output bit all bits in each port are set up for input at !RESET Peripheral register writing data may output data on port A or B reading data may input data from port A or B
Background image of page 8
Jie Hu, ECE/NJIT, Spring 2011 ECE252 L22-I/O.9 Programming 6821 Assume that 6821 PIA has a base address of $20000 $20000 as the shared address for peripheral register A and data direction register A
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 10
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/29/2012 for the course ECE 252 taught by Professor Rosenstark during the Spring '99 term at NJIT.

Page1 / 27

lecture22 - ECE252 Microprocessors Spring 2011 Lecture 22:...

This preview shows document pages 1 - 10. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online