lecture24

lecture24 - ECE252 Microprocessors Spring 2011 Lecture 24:...

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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.1 ECE252 Microprocessors Spring 2011 Lecture 24: Building a Working 68000 System Jie Hu http://web.njit.edu/~jhu/ece252/002
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.2 Block Diagram of Macintosh 512K Motherboard Processor 68000 I/O Interface 6522 Real- time clock Serial I/O 8530 Floppy disk controller System ROM RAM buffers and Mux PAL decoders Dynamic RAM 512KB Sound logic Video logic Speaker Video display Control signals Modem Printer Mouse Keyboard System bus Disk drive
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.3 Review of Last Lecture I/O System Design Serial data transfer
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.4 Today’s Lecture Building Single-Board Computer (SBC) The main parts of a single-board computer Custom circuitry design for major sections of SBC The operation of a software monitor program
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.5 Designing a Minimal Single-Board Computer Objective: to build a computer system at minimal cost that executes programs written in 68000 code Two part of the system design the design of the minimal system the design of a software monitor that allows user to enter 68000 code into memory, execute programs, and aid in debugging
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.6 Minimal System Requirements Four main hardware sections of the system: Timing CPU Memory Input/Output Questions need to be answered for designing a particular system: How fast should the CPU clock speed be? How much EPROM memory is needed? How much RAM memory is needed? Should we use static or dynamic RAM? What kind of I/O should be used – parallel, serial, or both? Do we want interrupt capability? Will future expansion (of memory, I/O, etc.) be required? What kind of software is required?
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.7 Designing the Hardware: Timing Section Timing section: provide the CPU with a nice, stable clock signal Clock signal is generated by digital oscillators Clock frequency selection determined by the operating frequency of the chosen CPU, also need to consider the EPROM/RAM speed
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Jie Hu, ECE/NJIT, Spring 2011 ECE252 L24-SBC.8 The Timing Section: Power-on Reset Circuitry The CPU needs to be properly reset at power-on in order to begin executing its main (monitor) program correctly Power-on reset circuitry: to provide the CPU with a reset pulse upon the application of power Two requirements for correctly resetting 68000 upon power-on
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This note was uploaded on 03/29/2012 for the course ECE 252 taught by Professor Rosenstark during the Spring '99 term at NJIT.

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lecture24 - ECE252 Microprocessors Spring 2011 Lecture 24:...

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