mod03-2up

mod03-2up - 12-02-12 CS 230 Introduction to Computers and...

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12-02-12 1 CS 230 - Winter 2012 3-1 CS 230 – Introduction to Computers and Computer Systems Module 3 – Machine Internals (Slides based on materials prepared by Martin Karsten ) CS 230 - Winter 2012 3-2 Overview basic control elements pipelining memory hierarchy I/O devices
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12-02-12 2 CS 230 - Winter 2012 3-3 Control programmable circuits multiple execution steps control vs. data path CS 230 - Winter 2012 3-4 Multiplexor simplest control element forwards X or Y signal, depending on S often spelled multiplex e r X Y S
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12-02-12 3 CS 230 - Winter 2012 3-5 Clock clock cycle: beat of computer clock signal electrical signals propagate fast but not infinitely fast gate delays stabilization for analog / digital conversion CS 230 - Winter 2012 3-6 Single Cycle Execution one instruction per clock cycle fixed cycle length must cover slowest instruction i.e., longest signalling path in processor complex instructions optimize common case? => how to improve throughput?
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12-02-12 4 CS 230 - Winter 2012 3-7 Pipelining analogy: laundry wash – dry – fold – put away analogy: industrial assembly line sequential vs. pipelined execution latency vs. throughput startup latency for individual operation vs. overall latency for sequence of operations CS 230 - Winter 2012 3-8 Pipelining
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12-02-12 5 CS 230 - Winter 2012 3-9 Typical Instruction Cycle IF: instruction fetch ID: instruction decode load register values into ALU EX: execute MEM: memory access access memory WB: write back write results back to registers CS 230 - Winter 2012 3-10 Pipelining Performance assume time for stages is 100ps for register read/write 200ps for other stages compare pipelined data path with single-cycle Instr Instr fetch Register read ALU op Memory access Register write Total time lw 200ps 100 ps 200ps 200ps 100 ps 800ps sw 200ps 100 ps 200ps 200ps 700ps R-format 200ps 100 ps 200ps 100 ps 600ps beq 200ps 100 ps 200ps 500ps
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12-02-12 6 CS 230 - Winter 2012 3-11 Pipeline Performance CS 230 - Winter 2012 3-12 Pipeline Speedup if all stages are balanced i.e., all take the same time time between instructions pipelined = time between instructions serial / # of stages if stages are not balanced, speedup is less speedup due to increased throughput latency for each instruction unchanged (maybe) even slowed down a bit
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12-02-12 7 CS 230 - Winter 2012 3-13 Instruction Set for Pipelining constant length instructions (fetch, decode) few instruction formats, source fields same register operands can be fetched while decoding memory operands only in load and store one memory access per instruction compute address during execute no separate stage needed CS 230 - Winter 2012 3-14 Pipeline Hazards instructions are not completely independent hazard: condition that blocks pipelined flow
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This note was uploaded on 04/01/2012 for the course CS 230 taught by Professor Bb during the Spring '11 term at Waterloo.

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mod03-2up - 12-02-12 CS 230 Introduction to Computers and...

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