Lecture 12 - The hardware interface

Lecture 12 - The hardware interface - ECE265 1 ECE 265...

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ECE 265 LECTURE 12 The Hardware Interface 11/17/2010 1 ECE265
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Joanne E. DeGroat, OSU Lecture Overview The Hardware Interface The pins Special Characteristics of the ports Software control of I/O Port lines REF: Chapters 1,6, and 9 plus the 68HC11 reference manual. 11/17/2010 2 ECE265
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Joanne E. DeGroat, OSU The hardware pins The hardware pins Power and Ground Timing Interrupt Port A – I/O lines (restricted in how used) Port B – Output extended addressing Port C – Bidirectional I/O Port D – 5 bit port for serial I/O Port E – 8 analog inputs 11/17/2010 ECE265 3
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Joanne E. DeGroat, OSU Accessing I/O ports This is a memory mapped architecture I/O done by writing to specific memory address The ports Port A – At address $1000 Used for either General-purpose I/O but 3 are Inputs/4 outputs/1 bidirectional Output compare Input capture Pulse-accumulator applications Linked with the internal timers on the 68HC11 (more later) 11/17/2010 ECE265 4
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Joanne E. DeGroat, OSU Port A The direction of Port A signal lines Note that 3 pins input 4 pins output 1 bidirectional 11/17/2010 ECE265 5
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The I/O ports Port B – at address $1004 An output port – has the dual use of being used for external addressing when the MPU is configured for extended memory mode. Port C – at address $1003 All the lines are bidirectional The Port C data direction register DDRC is at $1007 This register configures the direction of the pins of the port. 11/17/2010
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Lecture 12 - The hardware interface - ECE265 1 ECE 265...

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