427-CAD2 - CAD2 1-Bit Register Assignment To design a...

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CAD2 1-Bit Register Assignment To design a register cell. Description In this CAD assignment, you will design, layout and simulate a 1-bit register (flip-flop) cell. Your full-custom datapath will require a couple of multi-bit registers and you should design this 1-bit register as a bit-sliced component for this purpose. You probably won’t use this cell in your final datapath but this exercise will in- troduce you to complex leaf-cell design as well as datapath-style layout concepts. Note that once again you must work on your own for this assignment. Implementation It is often desirable to be able to reset asynchronously the state of the register to a known value (usually zero). A typical logic gate implementation of a positive edge triggered master-slave D flip-flop is shown in Figure 1. An example for a static CMOS transmission gate-based implementation is shown in Fig. 2. Use of this de- sign, or similar designs more adapted to CMOS technology, would result in many fewer transistors than the flip-flop of Fig. 1, and it is not recommended that Fig. 1 be used. Note that a conceptually simpler starting point would be a flip-flop composed of two latches (connected in master/slave configuration) like the master latch in Fig. 2. The flip-flop could be further compacted by using a dynamic or pseudo-dynamic style with two-phase or sin- gle-phase clocking, but we do not support these design styles for EECS427. At this time, Modelsim will not support dynamic circuits modeled at the switch level. Layout Considerations
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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427-CAD2 - CAD2 1-Bit Register Assignment To design a...

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