427-CAD3 - CAD3 The Register File Assignment To design a...

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CAD3 The Register File Assignment To design a Register File (RF) for your microprocessor. Description In this CAD assignment, you will design a 16-word, 16-bit RF with 1 write port and two read ports. One of the structures that is central to the datapath is an RF. An RF consists of a set of registers that can be read from or written to. Writing a register requires (i) an address, (ii) the data to be written and (iii) a signal that controls the write timing. Reading an RF can often be controlled by just the address but may include additional logic. The RF for this project is to include an array of flip-flops or latches and properly sized buffers for the associated read/write circuits. Address decode logic is not required in CAD3, but will have to be added to your design when the RF is integrated with the microprocessor control circuitry. Register Cell Conventionally, an RF would consist of an array of static RAM cells with read/write circuitry and a sense amplifier. Though this type of implementation yields a fast, compact design, it requires much design effort, especially for the sense amplifiers. In small RFs (few registers), the support circuitry for the SRAMs is used by a small number of registers, making the SRAM-based RF larger than some other types. An alternative approach is to use a latch consistent with your clocking scheme, modified to have two read ports and one write port. One such example is illustrated in Fig. 8.66 and Fig. 9.14 in the Weste text book. This method makes use of pass transistors at the input and the output with the decode control signals driving their gates. Alter- natively, tri-state buffers could be used to read the RF, and gated clocks could be used to write them. Another way to implement an RF is with multiplexors, as shown in Figure 1. While this implementation is conceptually simple, routing all of the mux inputs from the array cells to the muxes will create unnecessary routing bottlenecks. Figure 1: Register File Drivers and Buffers Control signals shared by all 16 bits of a register can have large capacitive loading compared to other signals in your design. The data output buses on the RF may also have large loading associated with them. These signals are candidates for transistor sizing on the gates that drive them or possibly even the insertion of buffers. In either case, these design decisions should be based on Eldo simulations. Course: 427 Page 1 of 4 CAD 3
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Bus Strategy You can use several methods to drive values onto the microcontroller buses. Two common ones that you can use in this class are multiple buses coming out of the RF with a mux to select the proper word. Another possibility is to have tristate drivers on the outputs of each component that can drive the bus. This will require only one bus. Note that true tristate buses require keeper latches if they have active gate inputs connected to them and are allowed to float to intermediate
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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427-CAD3 - CAD3 The Register File Assignment To design a...

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