427-CAD4 - CAD4 The ALU Assignment To design a 16-bit ALU...

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CAD4 The ALU Assignment To design a 16-bit ALU which will be used in the datapath of the microprocessor. This ALU must support two’s complement arithmetic and the instructions in the baseline architecture. Description The Arithmetic and Logic Unit (ALU) is the heart of your processor. The minimum set of instructions your ALU needs to support consists of (i) ADD, (ii) SUB, (iii)CMP, (iv) AND, (v) OR, and (vi) XOR. Your ALU must support both register-based operands and immediate operands. You can implement all the above instructions with the adder as the basic building block. A two’s complement subtracter and a comparator can be derived from the adder structure. Two’s complement subtraction (A - B) is implemented by adding A, B_bar, and 1 (Carry_in = 1). Compare functions (GE, LE), which are used to set processor flags for conditional branches, can be implemented with a subtracter and the information from the most significant bit (sign bit). Implementing “Less Than” is a little more complicated because of overflow problems. To detect a zero output, you need a NOR tree to verify that no result bit is a 1. There are two general approaches in designing the ALU. The first one is conceptually simpler but the sec- ond one may result in a more efficient implementation. 1. Separate Logic Blocks Your ALU must perform six different functions; this could be accomplished as shown below, with the adder unit performing three of these, and simple logic blocks performing the other three. Then a four-to-one mul- tiplexer (or tristate buffers) could be used to select the correct function. 4 TO 1 MUX XOR ADD / SUB / CMP OR AND Figure 1: Simple ALU approach. 2. Modified Ripple Carry Adder An alternative is to make the adder perform the logic functions as well as arithmetic functions. Consider the standard adder equations: Sum: S = ABC + AB'C' + A'B'C + A'BC' Carry: Cout = AB + BC + AC If we define Half sum: H = AB' + A'B then we could write the adder equations as Sum: S = HC' + H'C Carry: Cout = AB + HC From the equations it is clear that when C is held at logical 0, the sum output is an XOR of A and B. S = AB' + A'B (XOR operation) Also, when C is held at logical 0, then, Cout = AB (AND operation) When C is logic 1, then Course: 427 Page 1 of 6 CAD 4
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Cout = AB + A + B = A + B (OR operation) This shows that appropriate switching of the carry line between adder elements will give the ALU logical functions. An example block diagram is shown below. 00 XOR, AND 01 SUM, SUB 1 10 OR, XNOR 0 A B C in C out FA S o A B C in C out S o A B C in C out S o A B C in C out S o 1 0 1 0 1 0 0 SUM, SUB XOR, XNOR A0 1 AND, OR S0 B0 A1 S1 B1 A2 S2 B2 A3 S3 B3 Carry Out Figure 2: Merged arithmetic/Logic functions. 3. Adder Designs Any of a variety of 16-bit adder designs could be used in your processors. Whichever design you choose to implement, you would first build a 1-bit cell. Note that any number of such elements may be cascaded to form an adder of desired width.
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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427-CAD4 - CAD4 The ALU Assignment To design a 16-bit ALU...

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