427-CAD8 - EECS 427 CAD8 Control Unit Design Assignment To...

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EECS 427 1 CAD8 Control Unit Design Assignment To design the controller of your microprocessor. Description The first step in designing the controller is to identify and define the control lines, which you have already completed in CAD 7. The controller for the baseline architecture is simplified by the fact that all instructions are one word long. In the simplest implementation of the microcontroller, the decode can be done with no state machines. If state machines are used for jump and branch, or other instructions (e.g. interrupt pro- cessing) which require two cycles in the execute stage, the state machines can be trivially simple. Implementing the control in a pipelined machine which has a separate decode stage (unlike ours) means having the necessary logic to set the control bits to their respective values in each stage for each instruction. This is accomplished by decoding the opcode from the Instruction register and the condition bits (in case of a branch or jump) to create the control bits which are stored in the Control Register. These control bits dic- tate the function of the EXECUTE stage in the next cycle. Simple control is also required for the fetch stage, the details of which depend upon your timing scheme for memory access and write back. In the 427 Baseline Architecture, decode and execute are in the same stage (to avoid data dependencies). The decode is so simple and fast that it does not add much delay to the execute stage. You can implement the control (decode) logic without a control register, but be certain that any lines controlling writing to data memory or register files are hazard-free. Your data memory interface (and sometimes your program memory interface) will have associated control signals in addition to data and address buses. These control signals should also be driven by your control unit. You may also need a few flip-flops to save certain control bits for one more clock cycle; for example, if you write back results into the register file on the positive edge of the clock after the completion of the execute stage, you may need to latch the Write_Enable signal on the falling edge of the clock so that you do not use
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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427-CAD8 - EECS 427 CAD8 Control Unit Design Assignment To...

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