427-CAD9 - EECS 427 CAD9 Peripherals and Top-level...

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EECS 427 CAD9 Peripherals and Top-level Integration Assignment Design peripherals or additional functional blocks for your project. Complete final chip assembly, functional and physical verification. In short - finish your project! Description - Peripherals A microcontroller design attempts to realize a system on a chip, eliminating, to the extent it is practical, the need for any other integrated circuits. In cases requiring large memories, it may not be practical to put all of the memory on chip, and in our 427 projects, we are not including analog blocks on chip. But in most cases, all of the I/O functionality needed for the target application should be on the microcontroller. As a simple example, if the microcontroller is to work with a keypad and an LCD display, the keypad should not require any active circuits, and the display should be driven directly from the microcontroller. Most of your projects will need to incorporate one of the following peripheral devices: parallel I/O (for A/D or D/A interface, solenoid control, contact-closure input or output, etc.), serial I/O (asynchronous or synchronous), programmable timer, keypad controller, display driver, mouse input, printer output, floppy or hard disk interface, or special arithmetic functional unit. You must generate the control signals with proper timing for any of these interfaces. Multipliers, MACs or other units that are more tightly tied to the instruction set architecture are usually part of the core architecture and are not peripherals per se. They do not have any sort of interrupt interface wiith the core’s controller/datapath but are accessed directly via instructions in the ISA. You are free to use full-custom or synthesis/APR design techniques (or a combination of the two) for this assignment. Description - Top-level Integration Your top-level schematic should contain all of the following blocks: controller, datapath, peripherals and i/o pads. Note that you should place internal memories in a separate, higher level of hierarchy as explained in class. Once you have thoroughly verified this schematic in Modelsim, then you must complete the top-level layout and DRC/LVS. Procedure - Peripherals Since your applications are very different, each group’s work will be unique for this portion of the assignment. One feature of your work that may be similar is that you might use memory-mapped I/O, as defined by the instruction-set architecture. This means that data is read from peripheral devices using a LOAD instruction, and written to peripheral devices with a STORE instruction. The addresses for these peripheral devices are in a section of the data memory address space which is not used for memory. You must decide which space you are reserving for I/O devices. For example, in a system which needs only a little data memory, you could take the full top half of the address
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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427-CAD9 - EECS 427 CAD9 Peripherals and Top-level...

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