427-HW1 - EECS 427 Homework 1 Relevant sections to review:...

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EECS 427 Homework 1 Relevant sections to review: 3.3.2, 5.3, 5.4, 6.2, 7.1.1, 7.2.3 Default technology: the minimum drawn channel length = 0.25um, the effective channel length for L drawn of 0.25um is 0.2um, nominal V dd =2.5V, see table “CMOS (0.25um) – Unified Model” on inside back cover of Rabaey for other parameters. Unless otherwise specified assume that the junction capacitance of a MOSFET is equal to half of its gate-to-channel capacitance C gc (i.e., C db = C sb = C gc /2). Ignore overlap capacitances. Assume cutoff region when computing gate capacitance (Table 3-4) and note that the relevant channel length term for the capacitor area is the effective channel length. 1. In a CMOS inverter with minimum channel length transistors and W n =1um: a. Find W p such that V M 1V and t plh is minimized. b. Also, find t plh in this case when the total output capacitance is 10fF. Refer to Table 3.3 of Rabaey (pg 106) to help in computing delay. However, make the change that the table entries are for W=0.25um and L
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427-HW1 - EECS 427 Homework 1 Relevant sections to review:...

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