427-Quiz3 - Quiz 3 EECS 427: VLSI Design I CLOSED BOOK,...

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Quiz 3 EECS 427: VLSI Design I CLOSED BOOK, CLOSED NOTES!! Underlined text highlights the specific questions you need to answer. 1. (30 points) a) Is the following piece of Verilog code behavioral or structural ? module half_adder (a,b,sum,carry); input a, b; output sum, carry; reg sum, carry; always @ (a or b) begin carry = a & b; sum = a ^ b; end endmodule Course: 427 Page 1 of 6 Quiz 3
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b) Generate the complete set of test vectors to check for a stuck-at 0 fault at G3 in the circuit below (Figure 1). Figure 1 c) For a 3-input NAND gate, there are 8 possible single stuck-at faults and 8 possible input vectors. How many test vectors are actually needed to cover all possible faults? List them. Course: 427 Page 2 of 6 Quiz 3
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2. (40 points) a) Given the plot of CLK-Q delay vs. data arrival time and using the 4 data points shown, find minimum D-Q delay for this register. Taking the definition of setup time as the point at which CLK-Q delay rises 5% from nominal, what is the setup time of this register
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427-Quiz3 - Quiz 3 EECS 427: VLSI Design I CLOSED BOOK,...

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