427-Quiz4 - Quiz 4 EECS 427: VLSI Design I CLOSED BOOK,...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
Quiz 4 EECS 427: VLSI Design I CLOSED BOOK, CLOSED NOTES Underlined text highlights the specific parts of questions you need to answer. Please keep explanations as brief as possible while getting across the key point . This will demonstrate to me that you know the material well. 1. Qualitative (30 points, 6 each) a) What are the two primary reasons why memory yield is often low compared to standard logic circuits? b) Give two main reasons why leakage power in memory is potentially more significant than in logic. Course: 427 Page 1 of 7 Quiz 4
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
scaled technologies ? d) List two negative side effects associated with designing a clock distribution network with slew rates that are too fast . e) From a noise margin perspective is IR drop on the ground rail more of a problem for dynamic or static circuits? Why? Course: 427
Background image of page 2
Image of page 3
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

Page1 / 7

427-Quiz4 - Quiz 4 EECS 427: VLSI Design I CLOSED BOOK,...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online