CAD-Synthesis APR - EECS 427 Synthesis and APR Flow for...

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EECS 427 1 Synthesis and APR Flow for EECS 427 This document describes the standard cell synthesis and automatic place and route (APR) design flow for use in the design of your controller and peripheral blocks. Synopsys Design Compiler, accessed via the design_analyzer GUI and the dc_shell scripting language, will be used for synthesis and Cadence Silicon Ensemble will be used for APR. This document will take you through the synthesis and APR of an example design. Once you have completed this tutorial, you will be able to move on to your own design. The Example Design The example design is located at ’$TSMC25/parts/cells/tutorial’. It contains the verilog, dc, schem, and lay- out directories as described below. See the README in the tutorial directory for a better description of many of the files in those directories. The example design is somewhat similar to the one you will be building for your control unit. You will find occasional comments on how your control unit (or other verilog designs) may be different from the example design. The example design has been through this entire process and so all the files are there for you to see. We recommend you start with the verilog files and schematics and perform the whole flow yourself. If you get stuck or, to verify that you’re proceeding correctly, please review the files in the tutorial directory. Setup First, create a link in your home directory to the directory $TSMC25/parts/cells. This is done because some of the tools ( sedsm ) we will be using to not recognize environment variables properly (i.e. $TSMC25). This link will make for less typing when trying to link to certain files. % ln -s $TSMC25/parts/cells/ tsmc25cells Next, copy the setup file ’.synopsys_dc.setup’ to your home directory. After you copy the file, feel free to change the ’designer’ from "Wolverine" to your name or your group name. % cp ~/tsmc25cells/synopsys/.synopsys_dc.setup ~ Now, go into whichever directory you want to work in, and create a directory tutorial and create the directory structure as shown below. % cd <your PERSONAL (not your group’s) class workspace> % mkdir tutorial % cd tutorial % mkdir dc % mkdir layout % mkdir verilog % mkdir schem In the future, you will of course replace the ’tutorial’ directory with the part you are synthesizing and put it in your group space. Overview of Synthesis Design Flow The following steps are involved in the synthesis of a block: Create a functional verilog description of the block and verify its functionality using Modelsim. For a de- sign like the controller, you’ll want to verify it together with the datapath. You can either use da_ic (and Export Verilog) to generate structural verilog or write structural verilog yourself (like you do for testbench- es). Synthesize the functional verilog into a gate-level netlist composed of standard cells. This is done using
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This note was uploaded on 04/01/2012 for the course EECS 427 taught by Professor Prof during the Spring '12 term at University of Michigan-Dearborn.

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CAD-Synthesis APR - EECS 427 Synthesis and APR Flow for...

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