M16_2_EEM16_F11_L05

M16_2_EEM16_F11_L05 - vectors Obtain a high level...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #5 Ch 4: Description and Analysis of Gate Networks Prof. Danijela Cabric Fall 2011
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Ch 4: Description and Analysis of Gate Networks
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Hierarchical Implementation of a Module 3 On the logic level the lowest description is the network of gates
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Gate Network 4 Gates Connections or Nets External inputs External outputs
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Gate Networks 5
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Describing Gate Networks 6
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Net List: Tabular Description of Gate Networks 7
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Hardware Description Language 8
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Universal Set of Gates ± A set of gates using which any combinational system can be built ± Example: {AND, OR, NOT} 9
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More Examples of Universal Sets ± {AND, NOT} and {OR, NOT} 10
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Another Universal Set: {NAND} 11
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Mixed Logic Notation 12
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Additional Complex Gate Structures in CMOS 13
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Analysis of Gate Networks ± Functional analysis ± Obtain I/O switching expressions ± Obtain a tabular representation of the binary function (if few variables) ± Define high level input and output variables use codes to related them to bit
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Unformatted text preview: vectors Obtain a high level specification of the system Network characteristics input load factors fan out factors delays 14 Obtain Switching Expressions Assign names to each connection in the network Write switching expressions for each gate output Substitute all internal names to obtain external outputs in terms of external input 15 Example Gate Network for Analysis 16 Example (contd) 17 Analysis of Networks with NOT, NAND, and NOR 18 Another Example: A NOR Network 19 Analysis of Characteristics Load factor of a network input Fan out factor of a network output Size of the networks Network (propagation) delay Number of levels of a network Dynamic characteristics 20 Characteristics of a Family of CMOS Gates 21 Example Network 22 Example (contd.) 23 Network Delay: Longest Path 24 Timing Diagram from Network Analysis 25...
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M16_2_EEM16_F11_L05 - vectors Obtain a high level...

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