M16_2_EEM16_F11_L06

M16_2_EEM16_F11_L06 - EEM16/CSM51A:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #6 Ch 5: Design of Gate Networks Prof. Danijela Cabric Fall 2011
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Ch 5: Design of Combinational Systems: Two Level Gate Networks
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Design optimization ± Important real life design criteria ± Delay: the time from inputs changing to new correct stable output ± Size: area taken by the circuit (proxy: # of transistors) ± Other criterion: power, reliability, … 3
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Two Level Networks 4 Two types • AND-OR network: Sum of Products • OR-AND network: Product of Sums • Inputs in complemented and uncomplemented forms
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Two level networks with Different Costs for f(x2, x1, x0) = one set(3, 6, 7) 4 5
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Minimal Two Level Networks ± Goal: minimum area minimum # of transistors ± in real life, wires also cost area ± Algebraic definition: fewest # of literals and terms ± Each literal and term translates to a gate input, each of which translates to two transistors ± Inverters ignored 6
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Minimal Expressions 7
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Graphical Representation of Switching
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This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.

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M16_2_EEM16_F11_L06 - EEM16/CSM51A:...

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