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M16_2_EEM16_F11_L07

M16_2_EEM16_F11_L07 - EEM16/CSM51A Lecture#7 Ch5:...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #7 Ch 5: Design of Gate Networks Prof. Danijela Cabric Fall 2011
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Announcements ± Quiz #1 will take this week during your discussion section 2
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Agenda ± Design of two level networks ± Minimal two level networks ± Karnaugh maps ± Design of two level NAND NAND and NOR NOR networks 3
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Graphical Representation of Switching Functions: Karnaugh Maps (or K Maps) ± 2 dimensional arrays of cells represent switching functions or expressions ± n variables 2 n cells ± Each cell represents a minterm ± cell i = assignment i ± minterms differing in one variable are ajacent ± adjacency condition any set of 2 r adjacent rows or columns: assignments differ in r variables ± Useful graphical aid in simplifying expressions 4
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K Maps 5
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K Maps (n=1,2,3) 6
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K maps (n=4) 7
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K maps (n=5) 8
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Representation of Switching Functions 9
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Rectangles of 1 and 2 Cells and Sum of Products 10
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Rectangle of 4 Cells and Sum of Products ± Product term of n 2 literals < > rectangle of four adjacent 1 cells 11 ± Product term of n s literals < > rectangle of 2 s adjacent 1 cells
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Representation of Product of n (a+b) Variables 12
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M16_2_EEM16_F11_L07 - EEM16/CSM51A Lecture#7 Ch5:...

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