M16_2_EEM16_F11_L08

M16_2_EEM16_F11_L08 - ± Existing technologies have limitations on the fan ‐ in of gates ± The procedure essentially limited to the single ‐

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #8 Ch 5: Design of Gate Networks Ch 6.4: Networks with 2 input multiplexers Prof. Danijela Cabric Fall 2011
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Announcements ± Midterm is on Thursday Oct 27 ± In class ± Closed book ± Includes chapters 1,2,3,4,5 and 6.4 ± You are allowed to bring one sheet of paper 8”x11” (two sided) with your own notes ± Bring a calculator 2
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Agenda ± Design of two level NAND NAND and NOR NOR networks ± Programmable logic: PLAs and PALs ± Networks with 2 input multiplexers 3
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Two level NAND NAND and NOR NOR Networ ks ± AND OR and OR AND not efficient for implementation. Why? ± However, can easily convert AND OR to NAND NAND, and OR AND to NORNOR, which are efficient. ± de Morgan’s theorem 4
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AND OR to NAND NAND 5
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OR AND to NOR NOR 6
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Limitations of Two Level Networks ± The requirement of uncomplemented and complemented inputs if not satisfied, may need an additional levels of NOT gates ± A two level implementation of a function might require a larger number of gates and irregular connections
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Unformatted text preview: ± Existing technologies have limitations on the fan ‐ in of gates ± The procedure essentially limited to the single ‐ output case ± The cost criterion of minimizing the number of gates is not adequate for VLSI designs 7 Programmable modules ± Standard (fixed) structure ± Customized (programmed) for a particular functions ± during the last stage of fabrication ± when incorporated into a system ± Flexible use ± More expensive and slower than fixed ‐ function modules 8 Programmable Logic Array ‐ PLA 9 PLAs using MOS transistors 10 Implementation of Switching Functions using PLAs 11 PLA Implementation of BCD ‐ Gray Code Converter 12 PAL: Programmable module with Fixed OR ‐ array 13 Networks with 2 ‐ input Multiplexers 14 Implementation of Switching Functions with Network of MUXes 15 Design of Networks with MUXes 16 Design of Networks with MUXes 17 Example 18...
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This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.

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M16_2_EEM16_F11_L08 - ± Existing technologies have limitations on the fan ‐ in of gates ± The procedure essentially limited to the single ‐

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