M16_2_EEM16_F11_L10

# M16_2_EEM16_F11_L10 - 19 Example of Binary Coding 20...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #10 Ch 7: Sequential Systems Specifications Ch 8: Sequential Networks Prof. Danijela Cabric Fall 2011

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Agenda ± Review: Mealy and Moore machines ± State minimization ± Canonical form of sequential networks ± Latches and edge triggered cells, D flip flop 2
Mealy and Moore State Machine 3

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Same Behavior in Time: Equivalent Sequential Systems 4
Equivalent States 5

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Example 6
Example (contd) 7

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Procedure to Minimize Number of States 8
( i+1)-equivalent States 9

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( i+1)-equivalent States 10
( i+1)-equivalent States 11

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( i+1)-equivalent States 12
When to Stop? 13

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Procedure: Summary ± Obtain P1 (directly from the state table) ± Obtain Pi+1 from Pi ± by grouping states that are i equivalent ± and whose corresponding successors are i equivalent ± Terminate when Pi+1 = Pi ± Write the reduced table 14
Example 15

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Example(contd.) 16
Example (contd) 17

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Example (contd) 18
Binary Specification of Sequential Systems

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