M16_2_EEM16_F11_L11

M16_2_EEM16_F11_L11 - 16 Practical D Flip ‐ Flop 17...

Info iconThis preview shows pages 1–28. Sign up to view the full content.

View Full Document Right Arrow Icon
EEM16/CSM51A: Logic Design of Digital Systems Lecture #11 Ch 8: Sequential Networks Prof. Danijela Cabric Fall 2011
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Canonical Form of Sequential Networks 2
Background image of page 2
Mealy and Moore Machines 3
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Binary Implementation 4
Background image of page 4
Example 5
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Canonical Network for this Example 6
Background image of page 6
Storage element: Gated Latch – First Try 7
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Remembering a Bit 8
Background image of page 8
Gates with Feedback 9
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Problem with SR latch 10
Background image of page 10
D Latch using SR Latch 11
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Implementation using Transmission Gates 12
Background image of page 12
Limitations of Level Sensitive Latches 13
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Limitations of Level Sensitive Latches 14
Background image of page 14
Solution: Edge Triggered Cell (D Flip flop) 15
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Implementing D Flip Flop: Master Slave Latches
Background image of page 16
Background image of page 17

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 18
Background image of page 19

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 20
Background image of page 21

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 22
Background image of page 23

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 24
Background image of page 25

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 26
Background image of page 27

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Background image of page 28
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 16 Practical D Flip ‐ Flop 17 Design of Canonical Sequential Networks ± Transform the transition and output functions ± Specify a state register to hold the required number of states ± Design the required combinational network 18 Example 19 Example: Coding 20 Example: State Transition and Output Functions 21 Example: Implementation 22 SR Flip ‐ Flop 23 JK Flip ‐ Flop 24 T (Toggle) Flip ‐ Flop 25 Implementing one Flip ‐ flip Type with Another Example: T using JK 26 Flip ‐ Flop Set and Reset Inputs 27 Initial State 28...
View Full Document

This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.

Page1 / 28

M16_2_EEM16_F11_L11 - 16 Practical D Flip ‐ Flop 17...

This preview shows document pages 1 - 28. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online