M16_2_EEM16_F11_L12

M16_2_EEM16_F11_L12 - flops (b) Use the transition function...

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EEM16/CSM51A: Logic Design of Digital Systems Lecture #12 Ch 8: Sequential Networks Prof. Danijela Cabric Fall 2011
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Design of Sequential FF Networks Excitation functions E(Q(t),Q(t+1)) 2
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Excitation Functions 3
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The Design Procedure Obtain a binary description of the function Select the type of flip flop Determine the inputs to the flip flop (use the excitation function) Design a combinational network 4
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Example: Design Modulo 5 Counter 5
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Example (contd.) 6
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Example (contd.) 7
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Example (contd.) 8
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Example 9
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Example (contd.) 10
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Example (contd.) 11
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Analysis of Canonical Sequential Networks Analyze combinational network Determine the transition and the output functions Determine high level specification of state description output functions If desired (or required), determine time behavior 12
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Example 13
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Example (contd.) 14
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Example (contd.) 15
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Example (contd.) 16
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Analysis of Networks with Flip Flops Obtain the transition function of the network: (a) Determine the inputs to the flip
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Unformatted text preview: flops (b) Use the transition function of the flip flops to determine the next state Obtain the output function Determine a suitable high level specification 17 Example 18 Example (contd.) 19 Example (contd.) 20 Example 2: Analysis 21 Example (contd.) 22 Example (contd.) 23 Example (contd.) 24 Example (contd.) 25 Timing Parameters of D Flip Flop 26 Characteristics of a CMOS D Flip Flop (with only uncomplemented outputs) 27 Timing Characteristics of Sequential Networks 28 Network Hold Time 29 Network Propagation Time 30 Maximum Clock Frequency t in : time between triggering edge of clock and stabilization of input x t out : time between stabilization of output z and next clock triggering edge 31 Maximum Clock Frequency 32 Example 33 Clock Skew 34 Example 35 Example: Timing Parameters Propagation Delay from x to z 36...
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M16_2_EEM16_F11_L12 - flops (b) Use the transition function...

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