M16_2_EEM16-Syllabus-F11 - Oct 27 Thu Standard...

Electrical Engineering Department Fall 2011
EEM16 Logic Design of Digital Systems Prof. Danijela Cabric
Course Syllabus [email protected]/* <![CDATA[ */!function(t,e,r,n,c,a,p){try{t=document.currentScript||function(){for(t=document.getElementsByTagName('script'),e=t.length;e--;)if(t[e].getAttribute('data-cfhash'))return t[e]}();if(t&&(c=t.previousSibling)){p=t.parentNode;if(a=c.getAttribute('data-cfemail')){for(e='',r='0x'+a.substr(0,2)|0,n=2;a.length-n;n+=2)e+='%'+('0'+('0x'+a.substr(n,2)^r).toString(16)).slice(-2);p.replaceChild(document.createTextNode(decodeURIComponent(e)),c)}p.removeChild(t)}}catch(u){}}()/* ]]> */
Week Date Day Lecture Due Reading
1
Sep 22 Thu Introduction about Digital Systems Ch 1
2
Sep 27 Tue Combinational systems: Specification, Data
representation, Switching functions
Ch. 2.1-2.4.1
Appendix A
Sep 29 Thu
Combinational systems: Switching
expressions, Karnaugh maps
Ch. 2.4.2, 2.5,
2.6
3
Oct 4
Tue Combinational ICs: CMOS switches and
gates and their characteristics
Ch. 3
Oct 6 Thu Gate networks: Description and analysis HW 1 Ch. 4
4
Oct 11 Tue Gate networks: Design of two-level &
minimal networks; PLAs and PALs;
Ch. 5
Oct 13 Thu Sequential systems: Specifications, states,
time behavior, reduction of state set
HW 2 Ch. 7
5
Oct 18 Tue Sequential systems: Implementation,
canonical networks
Ch. 8
Oct 20 Thu Midterm (in class) Ch. 1-7
6
Oct 25 Tue Analysis and synthesis, sequential networks
with flip-flops
HW 3 Ch. 8