M16_2_M16_Discussion4

M16_2_M16_Discussion4 - number of zeros in the input. 4....

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UCLA Department of Electrical Engineering EEM16 – Fall 2011 Discussion4 1. Ex. 4.7 Show that the operation (gate) represented by the switching expression ± ²³ ´ ² ± ´ ²µ³ is universal. You can use constants 0 and 1. 2. With the help of Table 1, determine the worst case propagation delay of the network shown in the figure below. (Need to obtain low to high and high to low delays to determine the worst case). Assume that each network output is connected to an input with load factor 1.
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3. Ex. 4.11 Analyze the NAND network shown in the following figure. Obtain a reduced switching expression for the output. Give a high-level description in terms of the
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Unformatted text preview: number of zeros in the input. 4. Use a * gate that implements the following logic: X Y X*Y 0 0 1 0 1 1 1 0 0 1 1 1 To implement that gate network of the function: ) ) ) Hint: Simplify first and then draw the gate network. 5. Consider the following functions i. ) ) ii. ) ) Use K-maps to minimize the sum of products form and product of sums form for each of the two functions. Write the Boolean expressions that result....
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This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.

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M16_2_M16_Discussion4 - number of zeros in the input. 4....

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