M16_2_M16_Discussion4_Soln

M16_2_M16_Discussion4_Soln - UCLA Department of Electrical...

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Unformatted text preview: UCLA Department of Electrical Engineering EEM16 – Fall 2011 Discussion4 Solution 1. Ex. 4.7 2. The longest path is: (choose not because XOR gates have longer delay than AND gates) ( ( ) ) Gate ( ( Identifier XOR2 AND2 OR2 XOR2 ( ( X1 A2 O2 X2 ) ) ) ) ( ( Output Load 2 2 1.1 1 ) ) ( ( [ns] 0.372 0.224 0.161 0.336 ) ) ( ( ) ) [ns] 0.342 0.194 0.221 0.321 [ns] [ns] 3. Ex. 4.11 4. 5. ...
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This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.

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