M16_2_M16_Discussion8

M16_2_M16_Discussion8 - bit and the other with the...

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UCLA Department of Electrical Engineering EEM16 – Fall 2011 Discussion 8 1. Ex. 8.4 (timing analysis only) For the canonical sequential network shown in Figure 8.40, determine the timing factors (in terms of the timing factors of cells and gates) for ±² ³ ´µ¶ ±² and ·¸¹ ³ ´µº ±². 2. Ex. 8.11 Implement a sequential (bit-serial) binary adder/subtracter. A control input k indicates whether an addition ( k =1) or a subtraction ( k =0) is performed. 3. Ex. 8.12 Implement a sequential (bit-serial) binary magnitude comparator for 16-bit operands. Describe two implementations: one beginning with the most-significant
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Unformatted text preview: bit and the other with the least-significant bit. 4. Ex. 9.17 Implement a. An eight-bit simple shifter using multiplexers; b. An eight-bit bidirectional 3-shifter using multiplexers. 5. Ex. 9.22 Analyze the network shown in Figure 9.38 and design a gate network using AND, OR, XOR, and NOR gates that implements the same function. ( Hint: z =1 if the inputs to the decoder and the multiplexer are identical. Implement an equality comparator using XOR gates and one NOR.)...
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M16_2_M16_Discussion8 - bit and the other with the...

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