Unformatted text preview: 3. Ex. 10.24 Design a 8 x 4 binary multiplier using AND gates and four-bit adder modules. Use the AND gates to produce the partial products and the adders to add them. Determine the worst-case multiplier delay in terms of the module delays. 4. Ex. 11.3 Design a bit-serial arithmetic unit that performs addition and subtraction for 16-bit operands and result in the two’s complement system....
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This note was uploaded on 04/02/2012 for the course EE EEM16 taught by Professor Cabriv during the Fall '11 term at UCLA.
- Fall '11
- Electrical Engineering