This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: ECE 290 UNIVERSITY OF ILLINOIS Fall 2011 V. Kindratenko AT URBANACHAMPAIGN
M. C. Loui EXAMINATION #2 Monday, October 17, 201 1
7:00 to 8:00 pm. Closed book. One 81/2" x 11" sheet of notes allowed. No calculators or other electronic devices. This booklet contains 7 pages. Write your answers on these pages. Show your work. Use backs
of pages if necessary. The problems are not weighted equally. Budget your time accordingly. If you feel that a problem
is ambiguous, give your reasons and state your assumptions. For your convenience, the last page of this booklet contains the Boolean algebra identities and
the ﬂip—ﬂop tables. You may detach this page. Name: souKT lONS NetID: Indicate your section: ( ) AD2 Th9 Klingler
( ) AD3 Th 10 Kindratenko () AD4 Thll Klingler 1. (20%)
( ) ADS Th 12 Duwe
2. (24%)
( ) AD6 Th1 Loui
3. (20%)
( ) AD7 Th2 Zimmerman
4. (20%)
( ) AD8 Th3 Rogers
5. (16%)
( ) ADA Th4 Onyuksel Total (1 00%) Name: 2 Problem 1. (20%) You will develop a state diagram with one input variable w and one
output variable 2. The output is 1 if and only if the last four input bits are 1011 or the last three
input bits are 1 10. Note that these sequences may overlap. Sample input: 0 l 1
Required output: 0 0 0 (a) (16 pts.) Draw the state diagram. Label each arc with w/z. Label the initial state with A and
other states with B, C, D, etc., as needed. Explain the purpose of each state. Use a minimum
number of states. Solutions with more than ten states are unacceptable. Purpose of each state: Ar“” N  Wﬁﬁuoum‘luo W) B: \‘“\
C: “to"alm (b) (4 pts.) What is the minimum number of ﬂipﬂops necessary to implement this state diagram
by a sequential circuit? watts MW», WMJﬂW3KCf‘W Name: 3 Problem 2. (24%) The excitation table of a UV ﬂipﬂop is given below; three pairs of
U,V values are speciﬁed for the 1 to 1 state transition. (3) (8 pts.) Complete the nextstate table
of the UV ﬂipﬂop. Each entry should be 0, 1, Q, or Q’. (b) (8 pts.) You will implement a J K ﬂipﬂop
using a UV ﬂipﬂop, a 3:8 decoder, and as few
additional gates as possible. Complete this state
table and specify the inputs U and V of the UV
ﬂipﬂop, using don’tcares where possible. For
the 1 to 1 state transitions, choose U and V
inputs to simplify the circuit below. For your
convenience, Kamaugh maps are also provided. (c) (8 pts.) Draw the sequential circuit. Omit the clock input. Complements of J and K are not
immediately available, but 0 and 1 are available. 0
l
2
3
4
5
6
7 Name: 4 Problem 3. (20%) This combinational circuit has edgetriggered JK and D ﬂipﬂops,
which share a common ideal clock 6 (not shown), a combinational circuit H, and an AND—gate.
The circuit inputs are w, x and the circuit output is z. The delays in H and in the ANDgate are
negligible. Complete the timing diagram for Q2, .11, and 2. If the value of a signal is not completely
determined, then write “??” in the appropriate space. Tum—1 I 1. 3 4 5 Name: 5 Problem 4. (20%) (a) (8 pts.) Perform the following operations in 5bit two’s—
complement arithmetic; you may convert the subtraction into an addition. In each case indicate
whether overﬂow occurs. 01110 01110 otllo + 11011 — 11011 +00‘0‘
01001 10011 Overflow? Yes ( ) NM Overﬂow? Yes (X No ( ) (b) (12 pts.) An nbit arithmetic unit takes inputs A: am. a0 and B: b,,_1 be, interpreted as the
nbit two’scomplement representations of numbers. The control signals are k. , kg, and co (the
carryin to stage 0). At each stage 1', the inputs to the full adder are Qi=aikl'k0' +bikl +bi'ko a; b,‘ (i) Determine the function of A and (ii) Determine the values for the control
B produced by each of the following signals to produce each of the following
combinations of control signals: functions: k1 k0 c0 Function Function k. k0 co A plus 1 1 O O \
B minus 1 \ t O Name: 6 Problem 5. (16%) We examine the arithmetic unit of Problem 4(b) further. (a) (8 pts.) Implement the function q; = a, k. 'k0' + b,k1+ bi’ko using one 4:1 multiplexer and as few inverters b
as possible. Constants 0 and 1 are A
immediately available, but not the complements of input variables. MM, (b) (8 pts.) Assume each combinational circuit N produces the outputs p, and qi exactly 5 ns
(nanoseconds) after the inputs are stable. Assume each full adder is implemented by the circuit
shown below. The delay in each gate below is 2 ns. Determine the time required to obtain the entire nbit output f,,_. 1?), as a function of n. Show
your reasoning. ...
View
Full Document
 Spring '08
 Staff

Click to edit the document details