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ECE_15A_Homework_7_Solutions

ECE_15A_Homework_7_Solutions - ECE 15A Winter 2012 Homework...

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Mustafa ECE 15A Winter 2012 Homework # 7 Solutions 1) (15p) Design a combinational circuit with four inputs, x, y, w, and z, and four outputs: A, B, C, and D. When the binary input value in decimal is 6,7,14 or 15, the binary output value is one less than the input value, otherwise it is one greater than the input. Solution 1: The following is the K-maps for each of the four outputs. It is easier to consider each input combination. When xywz = 0000, ABCD = 0001, so we put these four bits to top-left squares. Proceeding similarly, we fill K-maps as follows: (Only 1’s are shown) It should be straightforward to find the expressions for these K-maps. Finally, we draw our AND-OR circuits for these SOP expressions: 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 A = x B = y + wz C = w’z + yz + y’wz D = z’ 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 1 xy wz 00 01 11 10 00 01 11 10 A B C D

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Mustafa 2) (10p) A majority circuit is a combinational circuit whose output is equal to 1 if the input variables have more 1’s than 0’s. The output is 0 otherwise. Design a 6-input majority circuit. Solution 1: In this problem we can draw a 6 variable K-map and find a minimal expression from that K-map. Below are the results for this method (Inputs are ABCDEF). Here all the minterms except red ones bring an essential prime implicant that covers 4 minterms. The minimal SOP expression is then found as: F = ABCD + ABCE + ABCF + ABDE + ABDF + ABEF + ACDE + ACDF + ABEF + ADEF + ACEF + BCEF + CDEF +BCDE + BCDF Observe that we have every possible 4-input combination in this result, which makes sense (we could have guessed it). This requires 15 4-input AND gates and a single 15-input OR gate, or 5 OR gates if we are allowed at most 4-input gates. We can, however, simplify the expression as follows (again, this expression makes sense actually): F = ABC(D+E+F) + DEF(A+B+C) + (AB+AC+BC)(DE+DF+EF) The circuit diagram for this expression is given below (uses 14 gates): 1 AB CD 00 01 11
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ECE_15A_Homework_7_Solutions - ECE 15A Winter 2012 Homework...

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