homework_6_ece15a_12 - 5. (10p) Complete the timing diagram...

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Homework #6 February 14, 2012 1 Homework #6 due February 27 at noon ECE 15a Winter 2012 1. (5p) Simplify the following expression and implement it with NOR gates only. Assume that both true and complement versions of the input variables are available. F(W,X,Y,Z) = WX’+WXZ+W’Y’Z’+W’XY’+WXZ’ 2. Convert the circuit shown in Figure 1 to (5p) (a) all NAND gates, (5p) (b) all NOR gates, by adding bubbles and inverters where necessary. 3. (5p) Draw the NAND logic diagram for the following expression, using a multiple-level NAND cir- cuit: F(w,x,y,z) = w(x+y+z)+xyz 4. (5p) Realize Z=ab’(c+d+e’g(f’+h)) using NAND gates. Add inverters if necessary.
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Unformatted text preview: 5. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. a c g Z b d e h Figure 1 a c b d e Figure 2 f Homework #6 February 14, 2012 2 6. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,0,1,0) to (1,1,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. a Figure 3 b c d e f 0 5 10 20 30 40 50 60 70 80 90 100 110 120 3 3 5 1 3 4 x y z w a b c F d Figure 4....
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This note was uploaded on 04/04/2012 for the course ECE 15A taught by Professor M during the Spring '08 term at UCSB.

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homework_6_ece15a_12 - 5. (10p) Complete the timing diagram...

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