This preview shows pages 1–2. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: 5. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. a c g Z b d e h Figure 1 a c b d e Figure 2 f Homework #6 February 14, 2012 2 6. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,0,1,0) to (1,1,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. a Figure 3 b c d e f 0 5 10 20 30 40 50 60 70 80 90 100 110 120 3 3 5 1 3 4 x y z w a b c F d Figure 4....
View Full Document
This note was uploaded on 04/04/2012 for the course ECE 15A taught by Professor M during the Spring '08 term at UCSB.
- Spring '08