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Unformatted text preview: The NAND diagram is shown below: X X Y Y Z Z W F 4. (5p) Realize Z=ab(c +d+e g(f+h)) using N AND gates. Add inverters if necessary. Solution: a b c d e g f h a b c d e g f h Z Z 5. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. Solution: 7. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,0,1,0) to (1,1,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. Solution: X Y Z W Y A B C D F 0 1 2 3 4 5 6 7 8 9 10 11 12 13...
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This note was uploaded on 04/04/2012 for the course ECE 15A taught by Professor M during the Spring '08 term at UCSB.
 Spring '08
 M
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