hw6_solution

hw6_solution - The NAND diagram is shown below: X X Y Y Z Z...

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Homework #6 ECE 15a Winter 2012 1. (5p) Simplify the following expression and implement it with NOR gates only. Assume that both true and complement versions of the input variables are available. F(W,X,Y,Z) = WX’+WXZ+W’Y’Z’+W’XY’+WXZ’ Solution: The Karnaugh map of this function is as follows: WX\YZ 00 01 11 10 00 1 01 1 1 11 1 1 1 1 10 1 1 1 1 Thus, F(W,X,Y,Z)= W+Y’Z’+XY’. The NOR gate implementation is shown below: W Y’ Z’ X W Y Z X’ F F 2. Convert the circuit shown in Figure 1 to (5p) (a) all NAND gates, (5p) (b) all NOR gates, by adding bubbles and inverters where necessary. Solution: (a) NAND gate implementation:
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a b c d e g f (b) Nor gate implementation a b c d e g f 3. (5p) Draw the NAND logic diagram for the following expression, using a multiple-level NAND circuit: F(w,x,y,z) = w(x+y+z)+xyz. Solution: ±²³ ´³ µ³ ¶· ¸ ±¹² º ±´ » µ » ¶·¼
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Unformatted text preview: The NAND diagram is shown below: X X Y Y Z Z W F 4. (5p) Realize Z=ab(c +d+e g(f+h)) using N AND gates. Add inverters if necessary. Solution: a b c d e g f h a b c d e g f h Z Z 5. (10p) Complete the timing diagram in Figure 3 for the circuit in Figure 2. Assume gate delays of 5ns. Solution: 7. (25p) Consider the circuit in Figure 4: Draw timing diagrams for the signals a,b,c,d and F after the inputs have switched at time t0 from(x,y,z,w) = (1,0,1,0) to (1,1,1,0). This circuit has a static hazard on c and a dynamic hazard on F. The numbers inside the gate symbols represent gate delays. Solution: X Y Z W Y A B C D F 0 1 2 3 4 5 6 7 8 9 10 11 12 13...
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This note was uploaded on 04/04/2012 for the course ECE 15A taught by Professor M during the Spring '08 term at UCSB.

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hw6_solution - The NAND diagram is shown below: X X Y Y Z Z...

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