cse325_S12_set_2_coldfire

cse325_S12_set_2_coldfire - 68K/Coldfire Processor Core and...

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68K/Coldfire Processor Core and ISA Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee [email protected] (480) 727-7507
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set 2 -- 2 68K/Coldfire Processor Core - Introduction q Starting from 6800 in 1974 v 8-bit data and 16-bit address CISC processor q Microcontrollers v 8-bit: HC05, HC11, HC08, RS08 (6-8 pins, 1K flash, 64byte RAM) v 16-bit: HC16, HC12, S12
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set 2 -- 3 68K/Coldfire Processor Core - Introduction q Microprocessors v 1st generation: 68000 (16/32) -- 1979 v 2nd generation: 68020/68030 (fully 32 bits) -- 1984 v 3rd generation: 68040/68050 (FPU, splict cache, fully pipelined)-- 1990 v 4th generation: 68060 (superscalar and multiple integer pipelines, abandoned in favor of the PowerPC chips ) -- 1994 q Coldfire: a variant of 68K starting from 1994 v “assembly source" compatible, variable-length RISC q Main differences between 68K and Coldfire v Missing addressing modes and instructions v Non-availability of word- and byte-forms of nearly all arithmetic and logical instructions v Many instructions act only on registers, not on memory v Restrictions on available addressing modes for particular instructions v Simplification of the supervisor-level programming model
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set 2 -- 4 Coldfire Processor Core - Introduction q Architecture v Version 2/2M – single-issue v Version 3 – single-Issue + pipelined local bus v Version 4/4e – limited superscalar v Version 5 – fully superscalar q Coldfire cores v Synthesizable, configurable, and parameterizable q Platform: v use defined and verified set of IP blocks as the foundation for a system-on-a-Chip (SoC) design. v CF5210 and Standard Product Platform (with crossbar switch) q Coldfire processors v based on the Coldfire cores with integration (memory, bus, and peripheral interfaces) that is common in embedded systems.
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set 2 -- 5 Version 2 Coldfire CPU Core q Variable-length RISC, clock multiplied core q Independent, decoupled pipelines for instruction fetch and operand execution q 6 user-accessible, 32-bit wide general purpose registers q 32-bit data bus q 32-bit address bus supporting a 4 Gigabyte linear addressing range q two-level branch acceleration mechanisms q Enhanced multiply-accumulate (EMAC) execute on 32 x 32 +_ 32 MAC operations q Vector base register to relocate the exception-vector table q 100 percent synthesizable and technology-independent designs
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cse325_S12_set_2_coldfire - 68K/Coldfire Processor Core and...

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