cse325_S12_set_4_GPIO

Cse325_S12_set_4_GPI - Coldfire 52259 Signals and IO Multiplexing Computer Science Engineering Department Arizona State University Tempe AZ 85287

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7/23 Coldfire 52259 Signals and IO Multiplexing Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee [email protected] (480) 727-7507
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set 4 -- 2 Coldfire 52259 Processor q 100 or 144-pin LQFP (Low Profile Quad Flat Pack packages ) q 144-ball MAPBGA (Multi-array Plastic Ball Grid Array) q 64Kb SRAM q 128Kb flash
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52259 100-pin Package q There are many I/O functions to connect to external signals and the number of pins in a chip is limited q Multiplex multiple I/O functions to one pin v primary function, v alternate functions, v general-purpose I/O q Pin function is set by the operating mode q Pin layout shows primary functions set 4-- 3
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52259 144-pin BGA Package set 4 -- 4
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set 4 -- 5 Coldfire GPIO q I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.
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set 4 -- 6 Coldfire Port Registers q Port Output Data Registers (PORT n ) v store the data to be driven on the corresponding port
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This note was uploaded on 04/06/2012 for the course CSE 325 taught by Professor Ye during the Spring '08 term at ASU.

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Cse325_S12_set_4_GPI - Coldfire 52259 Signals and IO Multiplexing Computer Science Engineering Department Arizona State University Tempe AZ 85287

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