cse325_S12_set_8_SPI_I2C

cse325_S12_set_8_SPI_I2C - 7/23 Inter-chip Serial...

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Unformatted text preview: 7/23 Inter-chip Serial Communication: SPI and I2C Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee [email protected] q A duplex, synchronous, serial communication between CPU and peripheral devices v Master mode and slave mode v Bi-directional mode v Synchronous serial clock q Signals: v MOSI: master out slave in v MISO: master in slave out v SS: select signal from master to slave v SCK: serial clock Serial Peripheral Interface (SPI) MOSI MISO SCK SS1 SS2 MOSI MISO SCK SS MOSI MISO SCK SS processor peripheral 2 peripheral 1 set 8 -- 2 SPI Operation q Data registers in the master and the slave form a distributed register. q When a data transfer operation is performed, this distributed register is serially shifted by the SCK clock from the master q Can shift in burst mode shift reg. shift reg. MOSI MISO transmit data reg receive data reg transmit data reg receive data reg set 8 -- 3 CPOL and CPHA (Polarity and Phase) q CPHA=0 – the first edge on the SCK line is used to clock the first data bit (the first bit of the data must be ready when selected) q CPHA=1 – if required, the first SCK edge before the first data bit becomes available at the data out pin set 8 -- 4 SPI Block Diagram set 8 -- 5 Queued SPI q Queues for transmitting and receiving data, and commands. q Programmable queue to support up to 16 transfers without user intervention. q NEWQP: Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer. q ENDQP: End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue. q CPTQP: Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed. q Indirect read/write – QAR[ADDR] and QDR q Wraparound enabling, chip select, etc. set 9 -- 6 Control of SPI q Mode and status v mode: master or slave. v enable v SPIF is asserted when the QSPI has completed all the commands in the queue. v transfer size, clock polarity and phase, baud rate v delays between serial transfers and clock signal q Interrupts v on SPIF v write collision in accessing RAM (by QSPI and CPU) v abort set 8 -- 7 Example 12-bit QSPI Transfer q 0xB308 QMR: set up 12-bit data words with the data shifted on the falling clock edge, and a QSPI_CLK frequency of 4.125 MHz (assuming a 66-MHz internal bus clock)....
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This note was uploaded on 04/06/2012 for the course CSE 325 taught by Professor Ye during the Spring '08 term at ASU.

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cse325_S12_set_8_SPI_I2C - 7/23 Inter-chip Serial...

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