hw3-solutions

Since the write buffer to l2 interface is 16 bytes

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Unformatted text preview: tes/clock. Thus, we can see that the write buffer to L2 interface limits the transfer rate in this scenario. So, a merging write buffer will fill each entry before writing to the L2 cache, thus writing 16 bytes per 4 clocks. A non-merging write buffer will write each entry after getting the 8 bytes from the process, thus writing 8 bytes per 4 clocks. Therefore the merging write buffer has a 2x speedup over the non-merging one. ALTERNATE: A steady state condition is the write buffer writing an entry every L2 cache access. A merging write buffe...
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