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VN-L - 24'uodulo Continuous(StatIn StatOut me StatIn output...

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Unformatted text preview: 24 'uodulo Continuous (StatIn, StatOut); me StatIn; - output StatOut; assign StatOut :- ~ StatIn; // Continuous assignment. endnodule // SYDthesizgd net-inst is shown inIFigure D : StutIn c StutOfi E- ' INRB ' ‘ anfitg 1r; umoqs s": asytqau pazgsaqquxs // . . etnpampue 'quaumfigsse tuxnpaaoxd fiuuootg // -"[ + 395315 = Juno.) (335915) a silent: {games [0:5] 53.: :qunog [ozg]'qnd:mo :qasexa [2:0] qndur :(zumoo ‘qasaxfl Bugxoorg e1:an 2’1 2'3 module NonBlocking (RegA, Mask, RegB); input [3:0] RegA, Mask; output [3:0] RegB; reg [3:01’RegB; always @ (RegA or Mask) RegB <= RegA & Mask; /,/ Non—blockingvprocedural assignment. enduodule // Synthesized netlist' is shown in Figure : Ref 2 Hum ' RNDZ RI 0 Re 6 Hum HNDZ Rafi! R931 Hfltkl RNDZ nodule Target (elk, 3691!, Raga, Mask); input Clk; input [3:0] RegA, Mask; output [3:0] Regs; rag {3:01 Regs; always 0 (90801190 Clk) Re‘gB <= Reg! 8: Mask; ondnodulo // Synthesized netlist is shown in Figure ‘ n mm: mm .. .l 1 mm film I is L . - mm mm .. .. I. . . mm: mm 5r nodule FullAdder (A, B, CarryIn, Sum, CarryOut); imt A, B, CarryIn; output Sum, Can-you; “nigh Sun: a (A " B) " Cara/In,- auign Cara/Out = (A a B) | (B & CarryIn) | (A & CarzyIn); _ «Mule , . , // Synthesized netlist is shown in Figure ' 3> 9-38 85:: 95 «8912 N553: mus.me fl 85,93 ma umwfluwn cwuflmmgugm \\ manned—Una u N vv €353qu L n unpung gamma “mambo? 3" 8 use—so £520qu mmuoa ash-3.. “3mg..ng .stfiums uMwflMunmumfioo 33603 :\N :\N . mud—mam E.” Esoam m4.” umeumd wouflmmnufinm \\ oauudfimfio 8555 AA mmNMumnfimE u mmmhumnh andde “ummnumfi S u S . guano . 3565. :"S yuan.“ «ammuumnfiwa 3:: Hanna “832.35 550.5 .mmNMuMQEmE unwamwnndwhmb 0.5503. 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PH N . unkmfifiHH— mufiQ II USCG Banana 3:00 “59:5 :8an R": as?“ :33 :18 £55 Luzon £035 .335 unmwmmusmfioonoz 0.253. f . mag a: Eran 9.7.. umflumn omnwmwfigw \\ . 3.5363 6.3%. u 3.63: 302 gamma 58¢ an": as...“ «whoum. use.“ ,. “aux SHE 33.5 “303 6.8%. ~55 #3333082 352. \II. re module ConditionalExpression (StartXM, ShiftVal, Reset, StopXM); input StartXM, ShiftVal, Reset; ' output StopXM; ‘ assign StopXM = (! Reset) ? Startm ." ShiftVal : StartXM l Sh.'1'.ftVa1; endmodule // Synthesized netlist‘ is shown in Figure . module my_and1(a,b,y); input a,b; output y; reg Y; [email protected](a) "l, if(a & ) else y = 0; endmodule module my_and2(a,b,y); input alb; output y; reg y; [email protected](a or b) V, if(a & b) Y — 17 else Y = 0; endmodule module test; reg A,B; wire Y1,Y2; integer i; my_andl gZ(A,B,Yl); my_and2 g3(A,B,Y2); initial begin for (i=0 ; i<=3 ; i=i+l) begin ' {A,B}=i; #5; end end initial #20 $finish; endmodule {3'25 module SelectOneOf (A, B, Z); input [1:0] A, B; output [1:0] Z; reg [1:0] Z; - always (:1 (A or B) if (A > B) sndmodule z’zL module Compute (Marks, Grade); input [1:4] Marks; putput [0:1] Grade; reg [0:1] Grade; parameter FAIL = 1, PASS = 2, EXCELLENT = 3; always @ (Marks) if (Marks < 5) Grade = FAIL; else if ((Marks >= 5) 8: (Marks < 10)) ' Grade .= PASS; ondmodule 2’27 module ComputerLatch (Marks, Grade); input [1:4] Marks; output [0:1] Grade; reg [0:1] Grade; parameter FAIL = 1, PASS = 2 , EXCELLENT = 3; always @ (marks) if (Marks < 5) Grade = FAIL; else if ((Marks >= 5) && amarks < 10)) Grade = BASS; else Grade = EXCELLENT; ' endmodule Orgdefl Grade 1 nodule StateUpdate (CurrentState, zip); input [0:1] CurrentState; output [0:1] Zip; :eg [0:1] zip; parameter so = 0, 5'1 = 1. $2 = 2, S3 = 3; always a (CurrentState) caee (CurrentState) 50, 53: “Zip = 0; 51: Zip = 3;' endeaae enduodule CurmtStatoi always 6 (CurrentState) begin . 2.111: = 0; // This statement added. case (Gun-ants“ ta) endease end "i333 2’34 module NextStateLogic (NextToggle, Toggle); input [1:0] Toggle; output [1:0]-NextToggle; reg [1:0] NextToggle; always @ (Toggle) case (Toggle) 2'b01 : NextToggle = 2'b10,- 2'b10 : NextToggle = 2'b01; endcase enamodule FDlSlD 2'55 modulo NextStateLogicFullCase (NextToggle, Toggle); input [1:0] Toggle; output: [1:0] NextToggle; reg [1:0] NextToggle; always 6 (Toggle) $ case (Toggle) // synthesis full_case 2'b01 : NextToggle = 2'b10; 2 'b10 : NextToggle = 2'b01; endcase endmodule 9"“. F") nodule Priori tyLogic (NextToggle, Toggle); input [2:0] Toggle; output [2:0] Nexta'oggle; reg [2:0] NextToggle; 11ml 0 (Toggle) can; (Toggle) 3'bxx1 : NextToggle = 3'b010; 3'bx1x : NextToggle = 3 'b110; 3'b1xx : NextToggle = 3'b001; default : NextToggle = 3 'booo; abacus ondnodulo if (ToggleIO == -b1) NextToggle = 3 'b010; '. also if '(a‘ogglelll a: I131) NextTaggle = 3 'b110; also if (ToggleIZl == 11,1) NextToggle; 3 '5001; else ' NeXtTOlee = 3 'bOOO; 2’ 57 W modulo ParallelCase (NextToggle, Toggle); \ input [2:0] Toggle; output: [2:0] NextToggle; rag [2:0] NextToggle; always @ (Toggle) caaex (Toggle) // synthesis parallel_case 3 'bxxl : NextToggle = 3'b010; 3'bx1x : NextToggle = 3'b110; 3'b1xx : NextToggle= 3'b001._; default : NextToggle = 3'b000; endcase enamodule if (Toggle[O] == 'bl) NextToggle = 3'b010; if (Toggle[1] == 'bl) NextToggle = 3 'b110; if (Toggle[2] == 'bl) } NextToggle = 3 'b001; if ((Toggle[O] != 'bl) && (Toggle[1] != 'b1) && (Toggle[2] != 'b1)) NextToggle = 3 'b000; NextTogg lal_ w NextToggleZ . . INRB INRB ' T - - 132 h. w NextToggIea 0 o ' INRB INRB 2'44 _ output: [3:0] Line; reg [3:0] Line; integer J; always (4 (Address) for (J=3; J>=0;J=J—1) if (Address == J) .LineIJ] = 1; else Line[J] = 0; endmodule ‘ LineS - . Rddroecfl Hddrossl When the for-loop is expanded, the following four if statements are ob- ufined. if (Address == 3) Linel3] = 1; else Line[3] = 0; if (Address == 2) LinelZ] = 1; else Line[2] = 0; if (Address == 1) Linen] = 1; else Linell] = 0, if (Address == 0) LineIO] = 1; else LineIO] = 0; -4- 10nc olfi cycle 7 I. Q Dlttetent Input constraints . Constraining combinational outputs that drive combinational Inputs ...
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