achieving-timing-closure

achieving-timing-closure - Achieving Timing Closure...

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Achieving Timing Closure
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Achieving Timing Closure - 2 © Copyright 2010 Xilinx Objectives After completing this module, you will be able to: Describe a flow for obtaining timing closure Interpret a timing report and determine the cause of timing errors Apply Timing Analyzer report options to create customized timing reports
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Achieving Timing Closure - 3 © Copyright 2010 Xilinx Timing Closure
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Achieving Timing Closure - 4 © Copyright 2010 Xilinx Timing Reports Timing reports help you determine why your design fails to meet its constraints Reports contain detailed descriptions of paths that fail their constraints The implementation tools can create timing reports at two points in the design flow Post-Map Static Timing Report Use for an early indication as to whether your design might meet timing Post-Place & Route Static Timing Report Use as a final analysis of whether your design has met timing The Timing Analyzer is a utility for creating and reading timing reports
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Achieving Timing Closure - 5 © Copyright 2010 Xilinx Double-click Analyze Post-Place & Route Static Timing Opens the Post-Place & Route Static Timing Report Allows you to create custom reports Open a plain text version by clicking Static Timing Report in the Design Summary screen Using the Timing Analyzer
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Achieving Timing Closure - 6 © Copyright 2010 Xilinx Timing Analyzer GUI Hierarchical browser Quickly navigate to specific report sections Failing constraints indicated with a red “X” Timing objects window Summarizes the path displayed in the path detail window Report text Logic highlighted in blue can be cross-probed
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Achieving Timing Closure - 7 © Copyright 2010 Xilinx Cross-Probing Shows the placement of logic in a delay path Right-click on the delay path to see this option The FPGA Editor view is used for seeing the actual placement and routing used The Technology view shows logical path through components
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Achieving Timing Closure - 8 © Copyright 2010 Xilinx Timing Report Structure Timing constraints Number of paths covered and number of paths that failed for each constraint Detailed descriptions of the longest paths Data sheet report Setup, hold, and clock-to-out times for each I/O pin Timing summary Timing errors (number of failing paths) Timing score (total number of ps of all constraints that were missed) Timing report description Allows you to easily duplicate the report
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Achieving Timing Closure - 9 © Copyright 2010 Xilinx Paths Reported Setup paths Slowest delay paths for each constraint Defaults to the three longest paths Hold paths Fastest delay paths for each constraint Component switching limits Checks that the toggle rate and duty cycle are in limits with specification
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Achieving Timing Closure - 10 © Copyright 2010 Xilinx Report Example Constraint summary Number of paths analyzed Number of timing errors Length of critical path
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