January 31, 2008 - signal wire5 std_logic begin Y<=(not...

Info iconThis preview shows pages 1–3. Sign up to view the full content.

View Full Document Right Arrow Icon
EE 264 Introduction to Digital Design EE264_Sp2008 Page 1
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
entity Project1_VHDL is A : in std_logic; B : in std_logic; C : in std_logic; Y : out std_logic ); port ( end Project1_VHDL; EE264_Sp2008 Page 2
Background image of page 2
architecture dataflow of Project1_VHDL is signal wire1: std_logic; signal wire2: std_logic; signal wire3: std_logic; signal wire4: std_logic;
Background image of page 3
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: signal wire5: std_logic; begin-- Y <= (not A and not B and C) or (B and not C); This line is --- _ commented out wire1 <= not A; wire2 <= not B; wire3 <= not C; wire4 <= wire1 and wire2 and C; wire5 <= B and wire3; Y <= wire4 or wire5; end dataflow; EE264_Sp2008 Page 3...
View Full Document

This note was uploaded on 04/07/2008 for the course EE 264 taught by Professor Khondker during the Spring '08 term at Clarkson University .

Page1 / 3

January 31, 2008 - signal wire5 std_logic begin Y<=(not...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online