B x x x x x x 8 x x 9 i3 5 c x x x 11 x x x 10 x 12

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 1 2 3 4 5 6 7 8 9 PLA PLA A B C X X BC 3 X X X AB X AC 1 X X X 2 X X 4 X X X Fuse intact Fuse blown AB X CC B B AA X 0 1 F1 F2 Outputs + Inverters Flip-flops (Optional) O R P L AN E AND PLANE Inputs + (Buffers/Inverters) SPLD Structure SPLD Structure OTP & RP SPLDs OTP & RP SPLDs One time programmable (OTP) Re­Programmable (RP) CPLD CPLD Multiple PAL like blocks Reprogrammable Global Interconnects...
View Full Document

This note was uploaded on 09/23/2012 for the course CE 40223 taught by Professor Ejlaligoudarzi during the Spring '12 term at Sharif University of Technology.

Ask a homework question - tutors are online