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Unformatted text preview: 1 2 3 4 5 6 7 8 9 PLA PLA A B C X X BC 3 X X X AB X AC 1 X X X 2 X X 4 X X X Fuse intact Fuse blown AB X CC B B AA X 0 1 F1 F2 Outputs + Inverters Flip-flops (Optional) O R P L AN E AND PLANE Inputs + (Buffers/Inverters) SPLD Structure SPLD Structure OTP & RP SPLDs OTP & RP SPLDs One time programmable (OTP) Re­Programmable (RP) CPLD CPLD Multiple PAL like blocks Reprogrammable Global Interconnects...
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