Lab 6 Writeup (Graded) - Albert Ho ECE 315 Tuesday lab Lab...

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Albert Ho ECE 315 Tuesday lab Lab 06 writeup Objective: The purpose of this lab was to get some experience with a simple operational amplifier circuit. Equipment: Tektronix/Sony function generator PC –Waveform Manager Pro CA3046 IC (contains 3 standalone NPN Bipolar Junction Transistors, and a differential pair) ALD1117 IC (contains 2 p-channel bulk-tied MOSFETs) Breadboard, resistors, 0.1 μ F capacitor Experimental Results: Setup and Checking Using the integrated circuits available to us, we built the following circuit: Figure A : Circuit diagram for three stage operational amplifier
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We adjusted the value of R2 so that the voltage at the emitter of Q4 was within a few millivolts of 0 V. With the emitter voltage at around 100 mV, we found that we needed an R2 value of 50.45 k . To get the emitter voltage closer to 0 V, we needed to decrease the value of R2 slightly: we placed an 808 k in parallel with the 50.45 k resistor to realize this, which gave us: R2 = (808)(50.45)/(808+50.45) k = 47.485 k This R2 value gave us a Q4 emitter bias of around 20 mV. The Q4 base voltage was verified to indeed be 0.7 V above this value. We recorded the following voltage values at each node to verify that all the pMOSFETs were in saturation and NPNs in the forward active region of operation: Figure B : Circuit diagram for three stage operational amplifier with node voltages labeled These values were taken while V in1 and V in2 were biased to the circuit’s ground reference potential, because if they were not biased they would be undefined. The following copy of the circuit diagram shows the identification of the differential stage, gain stage and low-impedance output buffer stage. We identify the part of the circuit that performs differential to single-ended conversion as the gain stage, which is realized with the NPN Bipolar transistor Q3. We also have labeled the pMOSFET current sources M1, M2 and M3 at the top of the circuit as well as the current mirror realized by the NPN transistors Q1 and Q2:
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Figure C : Circuit diagram for three stage operational amplifier with stages identified and labeled Open Loop Voltage Gain and Output Resistance I. Differential Stage We configured the Tektronix function generator to output a triangle wave at a frequency of 100 Hz and amplitude 50 mV. We connected the input to V in1 and grounded V in2 . The connection to the base of Q3 was lifted and we obtained the following trace of the differential stage output Vout_diff with the 100 Hz input:
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Figure D : Time response waveform of 100 Hz triangle wave input and Vout_diff The output response in Figure D has raw values detailed in the following collection: Time (ms) Output (V) 0 -3.72E+00 1 -3.72E+00 2 -3.68E+00 3 -3.64E+00 4 -3.60E+00 5 -3.56E+00 6 -3.52E+00 7 -3.52E+00 8 -3.48E+00 With no external load, we make the following calculation for the open circuit voltage gain. The top waveform on Figure D is our input, which is plotted on a 50 mV/div scale. The bottom waveform on Figure D is our Vout_diff output, which is
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This lab report was uploaded on 09/24/2007 for the course ECE 3150 taught by Professor Spencer during the Spring '07 term at Cornell University (Engineering School).

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Lab 6 Writeup (Graded) - Albert Ho ECE 315 Tuesday lab Lab...

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