Albert Ho ECE 315 Tuesday lab Lab 06 writeup Objective: The purpose of this lab was to get some experience with a simple operational amplifier circuit. Equipment: Tektronix/Sony function generator PC –Waveform Manager Pro CA3046 IC (contains 3 standalone NPN Bipolar Junction Transistors, and a differential pair) ALD1117 IC (contains 2 p-channel bulk-tied MOSFETs) Breadboard, resistors, 0.1 μF capacitor Experimental Results: Setup and Checking Using the integrated circuits available to us, we built the following circuit: Figure A: Circuit diagram for three stage operational amplifier
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We adjusted the value of R2 so that the voltage at the emitter of Q4 was within a few millivolts of 0 V. With the emitter voltage at around 100 mV, we found that we needed an R2 value of 50.45 kΩ. To get the emitter voltage closer to 0 V, we needed to decrease the value of R2 slightly: we placed an 808 kΩin parallel with the 50.45 kΩresistor to realize this, which gave us: R2 = (808)(50.45)/(808+50.45) kΩ= 47.485 kΩThis R2 value gave us a Q4 emitter bias of around 20 mV. The Q4 base voltage was verified to indeed be 0.7 V above this value. We recorded the following voltage values at each node to verify that all the pMOSFETs were in saturation and NPNs in the forward active region of operation: Figure B: Circuit diagram for three stage operational amplifier with node voltages labeled These values were taken while Vin1and Vin2were biased to the circuit’s ground reference potential, because if they were not biased they would be undefined. The following copy of the circuit diagram shows the identification of the differential stage, gain stage and low-impedance output buffer stage. We identify the part of the circuit that performs differential to single-ended conversion as the gain stage, which is realized with the NPN Bipolar transistor Q3. We also have labeled the pMOSFET current sources M1, M2 and M3 at the top of the circuit as well as the current mirror realized by the NPN transistors Q1 and Q2: