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Lec14-Cache_measurement

Lec14-Cache_measurement - Cache Performance Measurement and...

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Cache Performance Measurement and Optimization CS61, Lecture 14 Prof. Stephen Chong October 18, 2011
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Stephen Chong, Harvard University Announcements HW 4: Malloc Final deadline Thursday You should have received comments on your design document Please seek a meeting or feedback from course staff if needed MMTMOH: Mammoth Multi-TF Malloc Of±ce Hours Wednesday evening. See website for details Midterm exam Thursday Oct 27 Practice exams posted on iSites (both College and Extension) 2
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Stephen Chong, Harvard University Mid-course evaluation 43 responses (122 enrolled students) Pace seems about right Some thought too slow, some thought too fast Making sections effective Not compulsory (no in-section quizzes) Section notes are available on website before section Generally on Friday Encouraged to look at notes before section, ±gure out where you need to focus Lecture videos available to all students Link from the schedule page Feedback HW1 feedback took time; assignments available for pickup in MD 143 HW2 and 3 (binary bomb and buffer bomb) feedback was automatic Will endeavor to give you timely feedback on remaining assignments 3
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Stephen Chong, Harvard University Dennis Ritchie ’63 Co-creator of C programming language Co-developer (with Ken Thompson) of UNIX operating system C is the foundation of UNIX Undergrad (‘63)and PhD (’68) at Harvard Worked at Bell Labs for 40 years Profound impact on computer science 4 1941-2011
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Stephen Chong, Harvard University 5 Topics for today Cache performance metrics Discovering your cache's size and performance The “Memory Mountain” Matrix multiply, six ways Blocked matrix multiplication Exploiting locality in your programs
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Stephen Chong, Harvard University 6 Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (# misses / # references) Typical numbers: 3-10% for L1 Can be quite small (e.g., < 1%) for L2, depending on size and locality. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: 1-2 clock cycles for L1; 5-20 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 50-200 cycles for main memory Average access time = hit time + (miss rate × miss penalty)
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Stephen Chong, Harvard University Wait, what do those numbers mean? Huge difference between a hit and a miss Could be 100x, if just L1 and main memory Would you believe 99% hits is twice as good as 97%? Consider: cache hit time of 1 cycle miss penalty of 100 cycles Average access time: 97% hits: 1 cycle + 0.03 * 100 cycles = 4 cycles 99% hits: 1 cycle + 0.01 * 100 cycles = 2 cycles This is why “miss rate” is used instead of “hit rate” 7
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Stephen Chong, Harvard University 8 Writing Cache Friendly Code Repeated references to variables are good ( temporal locality ) Stride-1 reference patterns are good (
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