Unformatted text preview: ) Vin D1 D2 D3 D4 V I 0
2 V 2 mA
ofEE100/42/43 SOLUTION TO HOMEWORK 8
f 5 V 5 mA
off 5 V 5 mA
The diode is on, when v >0. When the diode is on, I = V/1k.
he plot of V versusThe diode is off, when v <0. When the diode is off, I = 0.
Therefore, P10.39 (b)
The diode is on when v > 5V. When the diode is on, I = (V-5)/2k.
The diode is off when v < 5V. When the diode is off, I = 0.
Therefore, 382 (c)
When V > 0, Diode A is on; Diode B is off. I = V/1k.
When V < 0, Diode A is off; Diode B is on. I = V/2k. 382 (d) When V > 0, Diode C is on; Diode B is off. I = V/1k.
When V < 0 or V=0, Diode C is off; Diode D is on. I = any negative value. But V can
only be zero because 0.40 short circuit uDiodeiD). igh if either or both of the inputs are high. If both
P1 of the (a) The o ( tput s h
inputs are low the ouput is low. This is an OR gate.
(b) The output is high only if both inputs are high. This is an AND gate
P10.41 When the sinusiodal source is positive, D2 is on and D1 is off. Then, we
have v o (t ) = 2.5 sin(2pt ). Therefore, P10.67
he output is ) igh if either or both of the inputs are high. If both
ts are low the ouput henow. diode is off, OR circuit looks like this:
W is l the This is an the gate.
The output is high only if both inputs are high. This is an AND gate.
en the sinusiodal source is positive, D2 is on and D1 is off. Then, we
v o (t ) = 2.5 sin(2pt ). en the source is negative, D1 is on and D2 is off. Then, we have
) = -2.5 sin(2pt ). V1 nonlinear two-terminal device is modeled by the piecewise-linear
From the circuit, we know, Vin e Vo.
roach, the equivalent circuit of the device for =ach linear segment
Because se diode itoff, V1 istance Vin
ists of a voltage source in the ries wis h a res> Vo (= . ).
From the circuit, V1 = 2V (voltage divider). Therefore, we have Vin < 2.
So, when Vin < 2, Vo = Vin.
From 1), we know when the diode is on, Vin > 2.
When the diode is on, the circuit looks like: v = Ra i +Va 383 By applying the KCL at the Vo node, we have: Then, we have: Vo = 0.5 Vin + 1.
So,when Vin > 2, Vo = 0.5 Vin +1.
Combining 1) and 2), we have: P10.67 TP10.68
1) A clamp circuit adds or subtracts a dc component to the input waveform
such that either the positive peak or the negative peak is forced to
as umdiode is off. The ned v looks An
Assumesthe e a predetermicircuitalue. like:example circuit that clamps the
positive peak to +5 V is shown below: From the circuit, we know
This Vx value will turn on the diode. Therefore, the assumption is wrong.
Assume the diode is on. The circuit looks like this: By applying KCL at node Vx, we have: Vx = 16/7 volts. Ix = Vx/4k = 4/7 (mA). Ix is positive, flowing from Vx to GND.
This Ix value is consistent with the assumption that the diode is on.
Therefore, Vx = 16/7 Volts; Ix = 4/7 (mA). P7.6
(a) 101.101b = 2^2+2^0 + 2^(-1) + 2^(-3) = 5.625
(a) 173 = 10101101b = 255o = ADh
(b) 299.5 = 100101011.1b = 453.4o = 12B.8h
(c) 735.75 = 1011011111.11b = 1337.6o = 2DF.Ch
(d) 313.0625 = 100111001.0001b = 471.04o = 139.1h
(e) 112.25 = 1110000.01b = 160.2o = 70.4h
(note: b=binary; o = octal; h = hexadecimal) ...
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- Fall '08
- Logic gate, Diode B, Thévenin's theorem, OR Gate