w6-one - 198:211 Computer Architecture Lecture 10 Fall 2012 l Topics:Chapter 3 l l l Assembly Language 3.2 Register Transfer 3.4 ALU 3.5 Assembly level

w6-one - 198:211 Computer Architecture Lecture 10 Fall 2012...

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198:211 Computer Architecture l Topics:Chapter 3 l Assembly Language 3.2 l Register Transfer 3.4 l ALU 3.5 Lecture 10 Fall 2012
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Assembly level Programming l We are now familiar with high level programming languages such as C and Java l Computers execute machine code l Compilers generate machine code from source code l We need to understand how the code actually executes on various machines (architectures) l Studying binary code is not very easy l At the same time, we need a language that mimics the machine level instructions and still readable (textual format) l Enter Assembly: compilers can generate an intermediate step of code called assembly code l Assemblers then convert assembly code to machine code
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(recall) Von Neumann Architecture l Model of a computer that used stores programs l Both Data and Program stored in memory l Allows the computer to be “Re-programmed” l CPU is central to the computer Control Unit Arithmetic and Logic (ALU) Output Unit Memory Unit CPU Data Control Input Unit
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Simplified hardware view MAR MDR C MAR: Memory Address Register also known as Program Counter MDR: Memory Data Register C: Control Switch; 0 is Load Or 1 is Store Store: Store contents of MDR to Memory address specified by MAR Load: Load into MDR contents of Memory address specified by MAR
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Fetch-execute cycle l Notation: [X] or (X) contents stored at location (memory address) contained in Register X l IR executes the instructions l Where are the operands? l As part of the execution, data may be transferred among various registers in the CPU as well as memory l Typical data movement instruction is MOV IR ç [PC] Execute [IR] PC ç PC +1
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Assembly programmer view l ALU: Arithmetic Logic Unit l IR: Instruction register l GPR: General Purpose Registers l PC: Program Counter l SP: Stack Pointer l BR: Base Register ALU GPR Status Flags SP PC Memory Object Code Instructions & Data IR BR
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MOV instruction l Most common instruction is data transfer instruction l Notation: mov S, D (contents of S becomes contents of D) l mov data from memory to register and register to memory l mov data between registers l Notation: registers are preceded by % sign l mov data to and from stack l mov constants to registers l Notation: constant preceded by $
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Data formats l Data is represented in different sizes l Byte 8 bits l E.g., Char l Word .. 16 bits (2 bytes) l E.g., Short int l Double Word (long or dword).. 32 bits ( 4 bytes) l E.g., float l QWORD .. 64 bits (8 bytes) l E.g., double l Instructions can operate on any data size l movl, movw, movb l Operates on doubleword, word, byte respectively
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Bit and byte order Little-endian
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x86 General purpose registers (8) EAX AX AH AL ECX CX CH CL EDX DX DH DL EBX BX BH BL ESP --Stack Pointer EBP --- Base register ESI EDI 16 BITS 32 BITS 8 BITS
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Registers l Registers are 32 bit (operations can access 16 bits, 8 bits within the register) l
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  • Fall '08
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  • Processor register, Machine code, Addressing mode, eax, l༆ , leal ebx

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