This preview shows page 1. Sign up to view the full content.
Unformatted text preview: ces for Conductors in 0.18 µm Process
given in lecture and in Weste and Eshraghian, calculate the following values for this circuit
net (assuming λ = 0.09µm):
(a) CL , the load capacitance (view the gates of the driven inverters as capacitors). Calculate
exact geometric areas for all wiring components of CL and use the appropriate coeﬃcients
below to ﬁnd all component capacitances. You need not apply all of the rules in the book
for unusual shapes. Just break the layout into rectangles and calculate load capacitance
based on rectangles.
1 (b) The output rise time tr for the bus driver.
(c) The output fall time tf for the bus driver.
(d) The maximum propagation delay through the interconnect wiring from the driver to the
load furthest away.
(e) Adjust this propagation delay to account for capacitive fringing ﬁeld eﬀects.
(f) The τav average gate delay for the bus driver.
(g) The total propagation delay (gate delay + propagation delay through the wire).
Show all calculations in detail in order to receive the maximum partial credit. Also, please
note that you must allow for the diﬀerent possibilities of transistors being on in the driving
logic gate. In order to receive maximum credit for this problem, you must show all of your
work. Use a ruler to measure the layout or edit the layout for cell homework4assignment07
in Cadence library /caip/u3/bushnell/tryme using layou...
View Full Document
- Fall '08