Assignment #04

18 m process material rs square metal1 008

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Unformatted text preview: ces for Conductors in 0.18 µm Process Material Rs (Ω/Square) Metal1 0.08 Polysilicon 10.0 Diffusion (n+) 10.0 Diffusion (p+) 10.0 given in lecture and in Weste and Eshraghian, calculate the following values for this circuit net (assuming λ = 0.09µm): (a) CL , the load capacitance (view the gates of the driven inverters as capacitors). Calculate exact geometric areas for all wiring components of CL and use the appropriate coefficients below to find all component capacitances. You need not apply all of the rules in the book for unusual shapes. Just break the layout into rectangles and calculate load capacitance based on rectangles. 1 (b) The output rise time tr for the bus driver. (c) The output fall time tf for the bus driver. (d) The maximum propagation delay through the interconnect wiring from the driver to the load furthest away. (e) Adjust this propagation delay to account for capacitive fringing field effects. (f) The τav average gate delay for the bus driver. (g) The total propagation delay (gate delay + propagation delay through the wire). Show all calculations in detail in order to receive the maximum partial credit. Also, please note that you must allow for the different possibilities of transistors being on in the driving logic gate. In order to receive maximum credit for this problem, you must show all of your work. Use a ruler to measure the layout or edit the layout for cell homework4assignment07 in Cadence library /caip/u3/bushnell/tryme using layou...
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