Assignment #04

# The people who get high grades on this assignment are

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Unformatted text preview: tPlus and use electronic rulers to measure this layout. The people who get high grades on this assignment are the ones who are fairly careful about modeling parasitics in the layout. 2. (Reduction of CMOS Propagation Delay in Long Buses.) Consider again the prior problem. Answer the following questions about the circuit: (a) Will it speed up the circuit to break the wire into two lengths and use a buﬀer (consisting of two cascaded inverters) in between the two lengths? In order to determine the answer, you must assume minimal wiring distance between the two static inverters making up the buﬀer. Also, you must recalculate all wiring delays for the ﬁrst wire segment and the second wire segment. If it pays to break the wire into two lengths, how much shorter will the new propagation delay be? Do not forget to include the eﬀect of the new buﬀer. (b) Would it be even better to break the wire into three lengths? 3. (Static CMOS Decoder Design.) Design a logic schematic, a transistor schematic, a sticks diagram, and a circuit layout (using the rules established in Assignment III) for a three-input, eight-output decoder. Use only CMOS transmission gates, pass transistors, and inverters. Important hint: Use a regular gate matrix layout style for this design. Use pchannel MOSFET’s to realize the conditions for decoding each output (pulling it to logic 1) when it is selected. Use a weak n-channel MOSFET transistor on each output to pull it down to logic 0 when it is not being decoded. Turn in the following items: a logic schematic (generated by Cadence), logic simulation results for all possible input combinations (generated by Cadence), a transistor schematic (generated by Cadence), analog simulation results for all possible input combinations (generated by Spectre), a layout (generated by Caden...
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