ce12_w08_hw1_sol

ce12_w08_hw1_sol - 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1...

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CMPE 12 Winter 2008 Name: SOLUTIONS Homework 1: Due January 23 Email: 1) (10 pts) What is wrong with these transistor diagrams? i) CMOS design only allows for PMOS to be used in the Pull up (top of the diagram) and for NMOS to be in the Pull down (bottom). ii) This design shorts when A, C, and D are on and B is turned off; the output is undefined when A, C, and D are turned off and B is turned on. 2) (15 pts) a) Create a truth table for this logical equation: A=(X'YZ)'(X'+Y+Z') X Y Z A 0 0 0
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Unformatted text preview: 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 b) Draw a system of NAND gates that represents the truth table. c) Count the number of transistors in your NAND system. 2 * 3 input NAND = 2 * (6 transistors) = 12 4 * 2 input NAND = 4 * (4 transistors) = 16 16 + 12 = 28 transistors 3) (15 pts) Using a D Flip-Flop and any logic gates, implement a sequential logic structure for the equation D=XZ'+(YXZ)'+Y'X+Q where Q is the output of the Flip-Flop, and D is the input of the Flip-Flop....
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