ce12_w08_hw2 - 2(10 pts Fill in the'q and'r outputs in this...

Info iconThis preview shows page 1. Sign up to view the full content.

View Full Document Right Arrow Icon
CMPE 12 Winter 2008 Name:________________ Homework 2: Due January 30 Email:________________ 1) (14 pts) Based on the logic diagram, answer these questions: a) (2) What circuit is this? b) (2) What would be more appropriate labels? (instead of A, B, X, Y) c) (10) Add more logic gates to make this a negative-edge triggered Flip-Flop.
Background image of page 1
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: 2) (10 pts) Fill in the 'q' and 'r' outputs in this timing diagram. (Note that the tringle at the clock input indicates a flip-flop) 3) (16 pts) Perform the following conversions: a) 325 10 to binary b) 111001001 2 to decimal c) 0x4C3 to octal d) 1062 7 to base 13...
View Full Document

This note was uploaded on 01/06/2009 for the course CMPE 12 taught by Professor Diblas during the Fall '08 term at UCSC.

Ask a homework question - tutors are online